ARM R4 Manuale Utente

ARM DDI 0363E

11-19

ID013010

Table 11-11 shows how the bit values correspond with the DTRRX and DTRTX functions.

The Watchpoint Fault Address Register (WFAR) is a read/write register that holds the address 
of the instruction that triggers the watchpoint.

Figure 11-6 shows the bit arrangement of the Watchpoint Fault Address Register.

Table 11-12 shows how the bit values correspond with the WFAR functions.

The processor supports efficient exception vector catching. The read/write Vector Catch 
Register controls this, as Figure 11-7 on page 11-20 shows.

[31:0]

Data

Reads the Data Transfer Register. This is read-only for the CP14 interface.

 Reads of the DTRRX through the coprocessor interface cause the DTRTXfull flag to be cleared. 
However, reads of the DTRRX through the APB port do not affect this flag.

[31:0]

Data

Writes the Data Transfer Register. This is write-only for the CP14 interface.

 Writes to the DTRTX through the coprocessor interface cause the DTRRXfull flag to be set. 
However, writes to the DTRTX through the APB port do not affect this flag.

Address

31

0

1

Reserved

[31:1]

Address

This is the address of the watchpointed instruction. When a watchpoint occurs in ARM state, the 
WFAR contains the address of the instruction causing it plus an offset of 

0x8

. When a watchpoint 

occurs in Thumb state, the offset is plus 

0x4

.

[0]

Reserved

RAZ.