ARM R4 Manuale Utente
Debug
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
11-30
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11.4.18 Device Power-down and Reset Control Register
The PRCR is a read/write register that controls reset and power-down related functionality.
Figure 11-14 shows the bit arrangement of the PRCR.
Figure 11-14 PRCR format
Table 11-23 shows how the bit values correspond with the Device Power down and Reset
Control Register functions.
Control Register functions.
11.4.19 Device Power-down and Reset Status Register
The PRSR is a read-only register that provides information about the reset and power-down
state of the processor.
state of the processor.
Figure 11-15 on page 11-31 shows the bit arrangement of the PRSR.
a. Cortex-R4 does not implement the Security Extensions, so all the debug features are considered
secure.
31
0
3
Reserved
2 1
Hold internal reset
Force internal reset
No Power-down
Table 11-23 PRCR functions
Bits
Field
Function
[31:3]
Reserved
Do not modify on writes. On reads, the value returns zero.
[2]
Hold internal
reset
reset
Hold internal reset bit. This bit can be used to prevent the processor from running again before
the debugger detects a power-down event and restores the state of the debug registers in the
processor. This bit does not have any effect on initial system power-up as nSYSPORESET
clears it.
0 = Do not hold internal reset on power-up or warm reset. This is the reset value.
1 = Hold the processor non-debug logic in reset on warm reset until this flag is cleared.
the debugger detects a power-down event and restores the state of the debug registers in the
processor. This bit does not have any effect on initial system power-up as nSYSPORESET
clears it.
0 = Do not hold internal reset on power-up or warm reset. This is the reset value.
1 = Hold the processor non-debug logic in reset on warm reset until this flag is cleared.
[1]
Force
internal reset
internal reset
When a 1 is written to this bit, the processor asserts the DBGRSTREQ output for four cycles.
You can connect this output to an external reset controller which, in turn, resets the processor.
You can connect this output to an external reset controller which, in turn, resets the processor.
[0]
No
power-down
power-down
When set to 1, the DBGNOPWRDWN output signal is HIGH. This output connects to the
system power controller and is interpreted as a request to operate in emulate mode. In this mode,
the processor is not actually powered down when requested by software or hardware
handshakes. This mode is useful when debugging applications on top of working operating
systems.
0 = DBGNOPWRDWN is LOW. This is the reset value
1 = DBGNOPWRDWN is HIGH.
system power controller and is interpreted as a request to operate in emulate mode. In this mode,
the processor is not actually powered down when requested by software or hardware
handshakes. This mode is useful when debugging applications on top of working operating
systems.
0 = DBGNOPWRDWN is LOW. This is the reset value
1 = DBGNOPWRDWN is HIGH.