ARM R4 Manuale Utente

ARM DDI 0363E

11-45

ID013010

The behavior of the PC and CPSR registers while the processor is in debug state is as follows:

•

The PC is frozen on entry to debug state. That is, it does not increment on the execution 
of ARM instructions. However, the processor still updates the PC as a response to 
instructions that explicitly modify the PC.

•

If the PC is read after the processor has entered debug state, it returns a value as described 
in Table 11-41 on page 11-44, depending on the previous state and the type of debug 
event.

•

If the debugger executes a sequence for writing a certain value to the PC and subsequently 
it forces the processor to restart without any additional write to the PC or CPSR, the 
execution starts at the address corresponding to the written value.

•

If the debugger forces the processor to restart without having performed a write to the PC, 
the restart address is Unpredictable.

•

If the debugger writes to the CPSR, subsequent reads from the PC return an Unpredictable 
value, and if it forces the processor to restart without having performed a write to the PC, 
the restart address is Unpredictable. However, CPSR reads after a CPSR write return the 
written value.

•

If the debugger writes to the PC, subsequent reads from the PC return an Unpredictable 
value.

•

If the debugger forces the processor to execute an instruction that writes to the PC and this 
instruction fails its condition codes, the PC is written with an Unpredictable value. That 
is, if the debugger forces the processor to restart, the restart address is Unpredictable. 
Also, if the debugger reads the PC, the read value is Unpredictable.

•

While the processor is in debug state, the CPSR does not change unless written to by an 
instruction. In particular, the CPSR IT execution state bits do not change on instruction 
execution. The CPSR IT execution state bits do not have any effects on instruction 
execution.

•

If the processor executes a data processing instruction with Rd==R15 and S==0, then 
alu-out[0] must equal the current value of the CPSR T bit, otherwise the processor 
behavior is Unpredictable.

Vector catch

RA+8

RA+4

Vector address.

External debug request signal 
activation

RA+8

RA+4

Address of the instruction where the execution resumes.

Debug state entry request command

RA+8

RA+4

Address of the instruction where the execution resumes.

OS unlock event

RA+8

RA+4

Address of the instruction where the execution resumes.

CTI debug request signal

RA+8

RA+4

Address of the instruction where the execution resumes.

a. This is the address of the instruction that the processor can execute first on debug exception return. The address of the 

instruction that hit the watchpoint is in the WFAR.