ARM R4 Manuale Utente

ARM DDI 0363E

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The processor has the following interfaces for external access:
•

•

•

For more information on these interfaces and how they are integrated into the system, see the 
AMBA 3 APB Protocol Specification and the CoreSight Architecture Specification.

AMBA APBv3 is used for debugging purposes. CoreSight is the ARM architecture for 
multi-processor trace and debug. CoreSight defines what debug and trace components are 
required and how they are connected. 

 The APB debug interface can also connect to a DAP-Lite. For more information on the 
DAP-Lite, see the CoreSight DAP-Lite Technical Reference Manual.

You can connect an ETM-R4 to the processor through the ETM interface. The ETM-R4 
provides instruction and data trace for the processor. For more information on how the ETM-R4 
connects to the processor, see the CoreSight ETM-R4 Technical Reference Manual.

All outputs are driven directly from a register unless specified otherwise. All signals are relative 
to CLKIN unless specified otherwise.

The ETM interface includes these signals:
•

an instruction interface

•

a data interface

•

an event interface

•

other connections to the ETM.

See ETM interface signals on page A-19 for information about the names of signals that form 
these interfaces. See Event bus interface on page 6-19 for more information about the event bus.

The test interface provides support for test during manufacture of the processor using Memory 
Built-In Self Test (MBIST). For more information on the test interface, see MBIST signals on 
page A-21. See the Cortex-R4 and Cortex-R4F Integration Manual for information about the 
timings of these signals.