ARM R4 Manuale Utente
Debug
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
11-52
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DBGSELFADDR
The DBGSELFADDR signal specifies bits [31:12] of the offset from the debug ROM physical
address to the physical address where the processor APB port is mapped to the base of the 4KB
debug register map. This is a configuration input and must be tied off or only change while the
processor is in reset.
address to the physical address where the processor APB port is mapped to the base of the 4KB
debug register map. This is a configuration input and must be tied off or only change while the
processor is in reset.
DBGSELFADDRV is the valid signal for DBGSELFADDR. If the offset cannot be
determined, DBGSELFADDR must be tied off to zero and DBGSELFADDRV must be tied
LOW. The value of these signals can be read from the Debug Self Address Register (DSAR).
determined, DBGSELFADDR must be tied off to zero and DBGSELFADDRV must be tied
LOW. The value of these signals can be read from the Debug Self Address Register (DSAR).
DBGRESTART
The DBGRESTART signal is used to bring the processor out of debug halt state. The processor
acknowledges DBGRESTART by asserting DBGRESTARTED, and then starts fetching
instructions when DBGRESTART is deasserted.
acknowledges DBGRESTART by asserting DBGRESTARTED, and then starts fetching
instructions when DBGRESTART is deasserted.
DBGRESTARTED
The processor asserts DBGRESTARTED in response to a DBGRESTART request, when it is
ready to exit debug halt state and return to normal run state.
ready to exit debug halt state and return to normal run state.
DBGTRIGGER
The processor asserts DBGTRIGGER to indicate that the system has accepted a debug request
and attempts to enter debug state. It is not a handshake for the EDBGRQ signal. If DBGACK
does not go HIGH following DBGTRIGGER, the memory system has stopped responding and
the processor has not entered debug state.
and attempts to enter debug state. It is not a handshake for the EDBGRQ signal. If DBGACK
does not go HIGH following DBGTRIGGER, the memory system has stopped responding and
the processor has not entered debug state.
Table A-13 on page A-17 shows the debug miscellaneous signals.
11.10.3 Authentication signals
Table 11-42 shows a list of the valid authentication signals and the associated debug
permissions. Authentication signals are used to configure the processor so its activity can only
be debugged or traced in a certain subset of processor modes.
permissions. Authentication signals are used to configure the processor so its activity can only
be debugged or traced in a certain subset of processor modes.
Changing the authentication signals
The NIDEN, and DBGEN input signals are either tied off to some fixed value or controlled by
some external device.
some external device.
Table 11-42 Authentication signal restrictions
DBGEN
a
a. When DBGEN is LOW, the processor behaves as if
DSCR[15:14] equals b00 with the exception that halting
debug events are ignored when this signal is LOW.
debug events are ignored when this signal is LOW.
NIDEN
Non-invasive debug permitted
in User and Privileged modes
in User and Privileged modes
0
0
No
X
1
Yes
1
0
Yes