ARM R4 Manuale Utente

ARM DDI 0363E

11-55

ID013010

There are two ways that an external debugger can send data to or receive data from the 
processor:

•

The debug communications channel, when the processor is not in debug state. It is defined 
as the set of resources used for communicating between the external debugger and 
software running on the processor.

•

The mechanism for forcing the processor to execute ARM instructions, when the 
processor is in debug state. For more information, see Executing instructions in debug 
state on page 11-46.

At the processor side, the debug communications channel resources are: 
•

CP14 Debug Register c5 (DTR)

•

CP14 Debug Register c1 (DSCR).

The ARMv7 debug architecture is implemented on the processor so that:

•

If a read of the CP14 DSCR returns 1 for the DTRTXfull flag:
—

a following read of the CP14 DTR returns valid data and DTRTXfull is cleared. No 
prefetch flush is required between these two CP14 instructions.

—

a following write to the CP14 DTR is Unpredictable.

•

If a read of the CP14 DSCR returns 0 for the DTRTXfull flag:
—

a following read of the CP14 DTR returns an Unpredictable value.

—

a following write to the CP14 DTR writes the intended 32-bit word, and sets 
DTRRXfull to 1. No prefetch flush is required between these two CP14 
instructions.

When Nonblocking mode is selected for DTR accesses, the following conditions are true for 
memory-mapped DSCR, memory-mapped DTRRX, and DTRTX registers:

•

If a read of the memory-mapped DSCR returns 0 for the DTRTXfull flag:
—

a following read of the memory-mapped DTRTX is ignored. For example, the 
content of DTRRXfull is unchanged and the read returns an Unpredictable value.

—

a following write of the memory-mapped DTRRX passes valid data to the processor 
and sets DTRTXfull to 1.

•

If a read of the memory-mapped DSCR returns 1 for the DTRTXfull flag:
—

a following read of the memory-mapped DTRTX returns valid data and clears 
DTRRXfull.

—

a following write of the memory-mapped DTRRX is ignored, that is, both 
DTRTXfull and DTRRX contents are unchanged.

The ARMv7 debug architecture does not support other uses of the DCC resources. In particular, 
the processor does not support the following:
•

CP14 DSCR[30:29] flags to access the memory-mapped DTRRX and DTRTX registers

•

polling memory-mapped DSCR[30:29] flags to access CP14 DTR.