ARM R4 Manuale Utente

ARM DDI 0363E

13-6

ID013010

This section describes:
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When bit [0] of the Integration Mode Control Register (ITCTRL) is set to b1: 

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Values written to the write-only Integration Test Registers map onto the specified outputs 
of the macrocell. For example, writing 

b1

 to ITMISCOUT[0] causes DBGACK to be 

asserted HIGH.

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Values read from the read-only Integration Test Registers correspond to the values of the 
specified inputs of the macrocell. For example, if you read ITMISCIN[9:8] you obtain 
the value of ETMEXTOUT[1:0].

When you perform integration testing or topology detection:

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You must ensure that the other ETM interface signals cannot change value during 
integration testing.

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ARM strongly recommends that the processor is halted while in debug state, because 
toggling input and output pins might have an unwanted effect on the operation of the 
processor. You must not set the ITCTRL Register until the processor has halted.
When the ITCTRL Register is set, the ETM interface stops trace output, and outputs the 
data written into the relevant integration registers.

After you perform integration testing or topology detection, that is, the Integration Mode 
Control Register has been set, the system must be reset. This is because the signals that are 
toggled can have an unwanted effect on connected devices. 

ITMISCIN

[11]

See ITMISCIN Register (Miscellaneous Inputs) on page 13-8

ITMISCIN

[9:8]

ITMISCIN

[5]

ITMISCIN

[2]

ITMISCIN

[1]

ITMISCIN

[0]