ARM R4 Manuale Utente

ARM DDI 0363E

14-14

ID013010

This section describes the cycle timing behavior of the 

UDIV

 and 

SDIV

 instructions.

The divider unit is separate to the main execute pipeline so the 

UDIV

 and 

SDIV

 instructions require 

one cycle to issue. They execute out-of-order relative to the rest of the pipeline, and require an 
additional issue cycle at the end of the divide operation to write the result to the destination 
register. This additional cycle is not required if the divide instruction fails its condition code. 

Result Latency for a 

UDIV

 instruction A divided by B is given by:

Result Latency for a 

SDIV

 instruction A divided by B is given by:

 •

A divide instruction that fails its condition code or attempts to divide by zero has a Result 
Latency of three.

•

The value of the (clz(B) - clz(A) + 1)/2 component of these equations must be rounded 
down.

•

The clz(x) function counts the number of leading zeros in the 32-bit value x. If x is 
negative, it is negated before this count occurs.

2

clz(B) - clz(A) + 1

,0

Result latency = 3 + 

max

(

) )

(

2

clz(B) - clz(A) + 1

,0

Result latency = 4 + 

max

(

) )

(