ARM R4 Manuale Utente

ARM DDI 0363E

A-13

ID013010

Table A-8 shows the ATCM port signals.

Table A-9 shows the B0TCM port signals.

Input

Data from ATCM

Input

Parity or ECC code from ATCM

Input

Error detected by ATCM

a

Input

Wait from ATCM

Input

Late error from ATCM

Input

Access to ATCM must be retried

Output

Parity formed from ATCM address output

b

Output

Enable for ATCM lower word, bit range [31:0]

Output

Enable for ATCM upper word, bit range [64:32]

Output

Write enable for ATCM

Output

Address for ATCM data RAM

Output

Byte strobes for direct write

Output

ATCM RAM access is sequential

Output

Write data for ATCM data RAM

Output

Write parity or ECC code for ATCM

Output

Determines access type:
b001 = Load/Store
b010 = Fetch
b100 = DMA
b100 = MBIST

c

.

a. This signal is ignored when bit [0] of the Auxiliary Control Register is set to 0, see c1, Auxiliary Control 

Register on page 4-38.

b. Only generated if the processor is configured to include TCM address bus parity.
c. The MBIST interface has no way of signalling a wait. If it is accessing the TCM, and the TCM signals a wait, 

the AXI slave pipeline stalls and the data arrives later. However, no signal is sent to the MBIST controller to 
indicate this.

Input

Data from B0TCM

Input

Parity or ECC code from B0TCM

Input

Error detected by B0TCM

a

Input

Wait from B0TCM