ARM R4 Manuale Utente
Processor Signal Descriptions
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
A-16
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A.7
Dual core interface signals
Table A-11 shows the dual redundant core interface signals.
Table A-11 Dual core interface signals
Signal
Direction
Clocking
Description
DCCMINP[7:0]
Input
-
a
a. Implementation-defined.
Dual core compare logic input control bus
DCCMOUT[7:0]
Output
-
Dual core compare logic output control bus
DCCMINP2[7:0]
Input
-
Dual core compare logic extra input control bus
b
b. Not available in r0px revisions of the processor.
DCCMOUT2[7:0]
Output
-
Dual core compare logic extra output control bus