ARM R4 Manuale Utente

ARM DDI 0363E

Glossary-1

ID013010

This glossary describes some of the terms and abbreviations used in this manual. Where terms can 
have several meanings, the meaning presented here is intended.

A mechanism that indicates to a processor that the value associated with a memory access is 
invalid. An abort can be caused by the external or internal memory system as a result of attempting 
to access invalid instruction or data memory. An abort is classified as either a Prefetch or Data 
Abort, and an internal or External Abort. 

See also Data Abort, External Abort and Prefetch Abort.

An abort model is the defined behavior of an ARM processor in response to a Data Abort exception. 
Different abort models behave differently with regard to load and store instructions that specify 
base register write-back.

A mechanism, shared by many different instructions, for generating values used by the instructions. 
For four of the ARM addressing modes, the values generated are memory addresses (which is the 
traditional role of an addressing mode). A fifth addressing mode generates values to be used as 
operands by data-processing instructions.

This is a bus protocol that supports separate address/control and data phases, unaligned data 
transfers using byte strobes, burst-based transactions with only start address issued, separate read 
and write data channels to enable low-cost DMA, ability to issue multiple outstanding addresses, 
out-of-order transaction completion, and easy addition of register stages to provide timing closure. 
The AXI protocol also includes optional extensions to cover signaling for low-power operation.

AXI is targeted at high performance, high clock frequency system designs and includes a number 
of features that make it very suitable for high speed sub-micron interconnect.