ARM R4 Manuale Utente

ARM DDI 0363E

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ID013010

This manual is for major revision 1 of the processor. At the time of release, this includes the 
r1p0, r1p1, r1p2, and r1p3 releases, although the vast majority of the information in this 
document will also be applicable to any future r1px releases. The following broadly describes 
the changes made in each subsequent revision of the processor:

Revision 1  Introduction of the ECC functional options and addition of the FPU options, to 

implement the Cortex-R4F processor.

 The r1p0 release was not generally available.

The Cortex-R4 processor contains a number of IDentification (ID) registers that enable software 
or a debugger to identify the processor as Cortex-R4, and the variant (major revision) and 
revision (minor revision) of the design. These registers are:

This register is accessible by software and identifies the part, the variant, and the 
revision. See c0, Main ID Register on page 4-14. A copy of this register can also 
be read by a debugger through the debug APB interface. See Processor ID 
Registers on page 11-32.

This register can be read by a debugger through the debug APB interface, and by 
software. It identifies the variant and revision. See CP14 c0, Debug ID Register 
on page 11-10.

These registers can be accessed through the debug APB interface only, and 
identify the revision number of the processor. See Debug Identification Registers 
on page 11-35.

When the build-configuration includes the floating point unit, this register 
identifies the revision number of the floating-point unit. See Floating-Point 
System ID Register, FPSID on page 12-5.

 

Floating point functionality is provided only with the Cortex-R4F processor.

The revision number of the processor, in the Peripheral ID and FPSID registers, is a single field 
that incorporates information about both major and minor revisions.