ARM R4 Manuale Utente

ARM DDI 0363E

2-7

ID013010

The processor has a total of 37 program registers:
•

31 general-purpose 32-bit registers

•

six 32-bit status registers.

These registers are not all accessible at the same time. The processor state and operating mode 
determine the registers that are available to the programmer.

In the processor the same register set is used in both the ARM and Thumb states. Sixteen general 
registers and one or two status registers are accessible at any time. In Privileged modes, 
alternative mode-specific banked registers become available. Figure 2-3 on page 2-9 shows the 
registers that are available in each mode.

The register set contains 16 directly-accessible registers, R0-R15. Another register, the Current 
Program Status Register (CPSR), contains condition code flags, status bits, and current mode 
bits. Registers R0-R12 are general-purpose registers that hold either data or address values. 
Registers R13, R14, R15, and the CPSR have these special functions: 

Software normally uses register R13 as a Stack Pointer (SP). The 

SRS

 and 

RFE

 instructions use Register R13.

Register R14 is used as the subroutine Link Register (LR).
Register R14 receives the return address when a Branch with Link (

BL

 or 

BLX

) instruction is executed.

You can use R14 as a general-purpose register at all other times. The 
corresponding banked registers R14_svc, R14_irq, R14_fiq, R14_abt, and 
R14_und similarly hold the return values when interrupts and exceptions 
are taken, or when 

BL

 or 

BLX

 instructions are executed within interrupt or 

exception routines.

Program Counter  Register R15 holds the PC:

•

in ARM state this is word-aligned

•

in Thumb state this is either word or halfword-aligned.

 

There are special cases for reading R15:
•

reading the address of the current instruction plus, either:
—

4 in Thumb state

—

8 in ARM state.

•

reading 

0x00000000

 (zero).

There are special cases for writing R15:
•

causing a branch to the address that was written to R15

•

ignoring the value that was written to R15

•

writing bits [31:28] of the value that was written to R15 to the 
condition flags in the CPSR, and ignoring bits [27:20] (used for the 

MRC

 instruction only).

You must not assume any of these special cases unless it is explicitly stated 
in the instruction description. Instead, you must treat instructions with 
register fields equal to R15 as Unpredictable.