ARM R4 Manuale Utente
Programmer’s Model
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
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2.7.11
The M bits
M[4:0] are the mode bits. These bits determine the processor operating mode as Table 2-3
shows.
shows.
Note
•
In Privileged mode an illegal value programmed into M[4:0] causes the processor to enter
System mode.
System mode.
•
In User mode M[4:0] can be read. Writes to M[4:0] are ignored.
2.7.12
Modification of PSR bits by MSR instructions
In architecture versions earlier than ARMv6,
MSR
instructions can modify the flags byte, bits
[31:24], of the CPSR in any mode, but the other three bytes are only modifiable in Privileged
modes.
modes.
In the ARMv7-R architecture each CPSR bit falls into one of these categories:
•
Bits that are freely modifiable from any mode, either directly by
MSR
instructions or by
other instructions whose side-effects include writing the specific bit or writing the entire
CPSR.
Bits in Figure 2-4 on page 2-10 that are in this category are N, Z, C, V, Q, GE[3:0], and E.
CPSR.
Bits in Figure 2-4 on page 2-10 that are in this category are N, Z, C, V, Q, GE[3:0], and E.
•
Bits that an
MSR
instruction must never modify, and so must only be written as a side-effect
of another instruction. If an
MSR
instruction tries to modify these bits, the results are
architecturally Unpredictable. In the processor these bits are not affected.
The bits in Figure 2-4 on page 2-10 that are in this category are the execution state bits
[26:24], [15:10], and [5].
The bits in Figure 2-4 on page 2-10 that are in this category are the execution state bits
[26:24], [15:10], and [5].
•
Bits that can only be modified from Privileged modes, and that instructions completely
protect from modification while the processor is in User mode. Entering a processor
exception is the only way to modify these bits while the processor is in User mode, as
described in Exceptions on page 2-16.
protect from modification while the processor is in User mode. Entering a processor
exception is the only way to modify these bits while the processor is in User mode, as
described in Exceptions on page 2-16.
Table 2-3 PSR mode bit values
M[4:0]
Mode
Visible state registers
Thumb ARM
b10000
User
R0–R7, R8-R12, SP, LR, PC, CPSR
R0–R14, PC, CPSR
b10001
FIQ
R0–R7, R8_fiq-R12_fiq, SP_fiq, LR_fiq PC,
CPSR, SPSR_fiq
CPSR, SPSR_fiq
R0–R7, R8_fiq–R14_fiq, PC, CPSR,
SPSR_fiq
SPSR_fiq
b10010
IRQ
R0–R7, R8-R12, SP_irq, LR_irq, PC, CPSR,
SPSR_irq
SPSR_irq
R0–R12, R13_irq, R14_irq, PC, CPSR,
SPSR_irq
SPSR_irq
b10011
Supervisor
R0–R7, R8-R12, SP_svc, LR_svc, PC, CPSR,
SPSR_svc
SPSR_svc
R0–R12, R13_svc, R14_svc, PC, CPSR,
SPSR_svc
SPSR_svc
b10111
Abort
R0–R7, R8-R12, SP_abt, LR_abt, PC, CPSR,
SPSR_abt
SPSR_abt
R0–R12, R13_abt, R14_abt, PC, CPSR,
SPSR_abt
SPSR_abt
b11011
Undefined
R0–R7, R8-R12, SP_und, LR_und, PC, CPSR,
SPSR_und
SPSR_und
R0–R12, R13_und, R14_und, PC, CPSR,
SPSR_und
SPSR_und
b11111
System
R0–R7, R8-R12, SP, LR, PC, CPSR
R0–R14, PC, CPSR