ARM R4 Manuale Utente

ARM DDI 0363E

2-25

ID013010

When an instruction is encountered which is UNDEFINED, or is for the VFP when the VFP is 
not enabled, the processor takes the Undefined instruction exception. Software can use this 
mechanism to extend the ARM instruction set by emulating UNDEFINED coprocessor 
instructions. UNDEFINED exceptions also occur when a 

UDIV

 or 

SDIV

 instruction is executed, 

the value in Rm is zero, and the DZ bit in the System Control Register is set.

If the handler is required to return after the instruction that caused the Undefined exception, it 
must:

•

Advance the IT execution state bits in the SPSR before restoring SPSR to CPSR. This is 
so that the correct condition codes are applied to the next instruction on return. The 
pseudo-code for advancing the IT bits is:

Mask = SPSR[11,10,26,25];
if (Mask != 0) {

Mask = Mask << 1;
SPSR[12,11,10,26,25] = Mask;
}

if (Mask[3:0] == 0) {

SPSR[15:12] = 0;

}

•

Obtain the instruction that caused the Undefined exception and return correctly after it. 
Exception handlers must also be aware of the potential for both 16-bit and 32-bit 
instructions in Thumb state.
After testing the SPSR and determining the instruction was executed in Thumb state, the 
Undefined handler must use the following pseudo-code or equivalent to obtain this 
information:

addr = R14_undef - 2
instr = Memory[addr,2]
if (instr >> 11) > 28 { /* 32-bit instruction */

 instr = (instr << 16) | Memory[addr+2,2]
 if (emulating, so return after instruction wanted) }
 R14_undef += 2 //

} //
}

After this, 

instr

 holds the instruction (in the range 

0x0000

-

0xE7FF

 for a 16-bit instruction, 

0xE8000000

-

0xFFFFFFFF

 for a 32-bit instruction), and the exception can be returned from 

using a 

MOVS PC, R14

 to return after it.

IRQs are disabled when an Undefined instruction trap occurs. For more information about 
Undefined instructions, see the ARM Architecture Reference Manual.

A breakpoint (BKPT) instruction operates as though the instruction causes a Prefetch Abort.

A breakpoint instruction does not cause the processor to take the Prefetch Abort exception until 
the instruction is to be executed. If the instruction is not executed, for example because a branch 
occurs while it is in the pipeline, the breakpoint does not take place.

After dealing with the breakpoint, the handler executes the following instruction irrespective of 
the processor operating state:

SUBS PC, R14_abt, #4

This action restores both the PC and the CPSR, and retries the breakpointed instruction.