ARM R4 Manuale Utente
Programmer’s Model
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
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2.10
Unaligned and mixed-endian data access support
The processor supports unaligned memory accesses. Unaligned memory accesses was
introduced with ARMv6. Bit [22] of c1, Control Register is always 1.
introduced with ARMv6. Bit [22] of c1, Control Register is always 1.
The processor supports byte-invariant big-endianness BE-8 and little-endianness LE. The
processor does not support word-invariant big-endianness BE-32. Bit [7] of c1, Control Register
is always 0.
processor does not support word-invariant big-endianness BE-32. Bit [7] of c1, Control Register
is always 0.
For more information on unaligned and mixed-endian data access support, see the ARM
Architecture Reference Manual.
Architecture Reference Manual.