ARM R4 Manuale Utente
Processor Initialization, Resets, and Clocking
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
3-6
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3.2
Resets
The processor has the following reset inputs:
nRESET
This signal is the main processor reset that initializes the majority of the
processor logic.
processor logic.
PRESETDBGn
This signal resets processor debug logic and CoreSight ETM-R4.
nSYSPORESET
This signal is the reset that initializes the entire processor, including CP14
debug logic and the APB debug logic. See CP14 registers reset on page
11-23 for information.
debug logic and the APB debug logic. See CP14 registers reset on page
11-23 for information.
nCPUHALT
This signal stops the processor from fetching instructions after reset.
All of these are active-LOW signals that reset logic in the processor. You must take care when
designing the logic to drive these reset signals.
designing the logic to drive these reset signals.
The processor synchronizes the resets to the relevant clock domains internally.