ARM R4 Manuale Utente
System Control Coprocessor
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
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Figure 4-5 System performance monitor registers
System performance monitoring counts system events, such as cache misses, pipeline stalls, and
other related features to enable system developers to profile the performance of their systems.
It can generate interrupts when the number of events reaches a given value.
other related features to enable system developers to profile the performance of their systems.
It can generate interrupts when the number of events reaches a given value.
For more information on the programmer’s model of the performance counters see the ARM
Architecture Reference Manual.
Architecture Reference Manual.
See Chapter 6 Events and Performance Monitor for more information on the registers.
4.1.7
System validation
The system validation registers extend the use of the system performance monitor registers to
provide some functions for validation. You must not use them for other purposes. The system
validation registers schedule and clear:
•
provide some functions for validation. You must not use them for other purposes. The system
validation registers schedule and clear:
•
resets
•
interrupts
•
fast interrupts
•
external debug requests.
The system validation registers consist of nine read/write registers and one write-only register.
Figure 4-6 shows the arrangement of registers.
Figure 4-6 shows the arrangement of registers.
Figure 4-6 System validation registers
Opcode_2
CRm
CRn
Opcode_1
c9
0
0
c12
Overflow Flag Status Register †
Count Enable Set Register †
Count Enable Clear Register †
Performance Monitor Control Register †
Event Select Register †
Performance Counter Selection Register †
Cycle Count Register †
Software Increment Register †
Interrupt Enable Clear Register
User Enable Register
Interrupt Enable Set Register
Performance Count Register †
1
2
3
4
5
0
c13
1
2
0
0
1
2
c14
0
Write-only
Accessible in User mode
Read-only
Read/write
† If enabled in User
Enable Register
0
c15
Opcode_2
Opcode_1
CRm
CRn
0
1
nVAL IRQ Enable Set Register †
nVAL FIQ Enable Set Register †
nVAL Reset Enable Set Register †
nVAL Debug Request Enable Set Register †
nVAL IRQ Enable Clear Register †
nVAL FIQ Enable Clear Register †
nVAL Debug Request Enable Clear Register †
Cache size override register
nVAL Reset Enable Clear Register †
Write-only
Accessible in User mode
Read-only
Read/write
† If enabled in User
Enable Register
c1
2
3
4
5
6
7
c14
0
0