Jameco Electronics 3000 Manuale Utente
User’s Manual
3
A Rabbit that is slaved to a master processor can operate entirely with volatile RAM,
depending on the master for a cold program boot.
depending on the master for a cold program boot.
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There are 56 parallel I/O lines (shared with serial ports). Some I/O lines are timer syn-
chronized, which permits precisely timed edges and pulses to be generated under com-
bined hardware and software control. Pulse-width modulation outputs are implemented
in addition to the timer-synchronization feature (see below).
chronized, which permits precisely timed edges and pulses to be generated under com-
bined hardware and software control. Pulse-width modulation outputs are implemented
in addition to the timer-synchronization feature (see below).
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Four pulse width modulated (PWM) outputs are implemented by special hardware. The
repetition frequency and the duty cycle can be varied over a wide range. The resolution
of the duty cycle is 1 part in 1024.
repetition frequency and the duty cycle can be varied over a wide range. The resolution
of the duty cycle is 1 part in 1024.
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There are six serial ports. All six serial ports can operate asynchronously in a variety of
commonly used operating modes. Four of the six ports (designated A, B, C, D) support
clocked serial communications suitable for interfacing with “SPI” devices and various
similar devices such as A/D converters and memories that use a clocked serial protocol.
Two of the ports, E and F, support HDLC/SDLC synchronous communication. These
ports have a 4-byte FIFO and can operate at a high data rate. Ports E and F also have a
digital phase-locked loop for clock recovery, and support popular data-encoding meth-
ods. High data rates are supported by all six serial ports. The asynchronous ports also
support the 9th bit network scheme as well as infrared transmission using the IRDA pro-
tocol. The IRDA protocol is also supported in SDLC format by the two ports that sup-
port SDLC.
commonly used operating modes. Four of the six ports (designated A, B, C, D) support
clocked serial communications suitable for interfacing with “SPI” devices and various
similar devices such as A/D converters and memories that use a clocked serial protocol.
Two of the ports, E and F, support HDLC/SDLC synchronous communication. These
ports have a 4-byte FIFO and can operate at a high data rate. Ports E and F also have a
digital phase-locked loop for clock recovery, and support popular data-encoding meth-
ods. High data rates are supported by all six serial ports. The asynchronous ports also
support the 9th bit network scheme as well as infrared transmission using the IRDA pro-
tocol. The IRDA protocol is also supported in SDLC format by the two ports that sup-
port SDLC.
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A slave port allows the Rabbit to be used as an intelligent peripheral device slaved to a
master processor. The 8-bit slave port has six 8-bit registers, 3 for each direction of
communication. Independent strobes and interrupts are used to control the slave port in
both directions. Only a Rabbit and a RAM chip are needed to construct a complete
slave system, if the clock and reset control are shared with the master processor
master processor. The 8-bit slave port has six 8-bit registers, 3 for each direction of
communication. Independent strobes and interrupts are used to control the slave port in
both directions. Only a Rabbit and a RAM chip are needed to construct a complete
slave system, if the clock and reset control are shared with the master processor
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There is an option to enable an auxiliary I/O bus that is separate from the memory bus.
The auxiliary I/O bus toggles only on I/O instructions. It reduces EMI and speeds the
operation of the memory bus, which only has to connect to memory chips when the
auxiliary I/O bus is used to connect I/O devices. This important feature makes memory
design easy and allows a more relaxed approach to interfacing I/O devices.
The auxiliary I/O bus toggles only on I/O instructions. It reduces EMI and speeds the
operation of the memory bus, which only has to connect to memory chips when the
auxiliary I/O bus is used to connect I/O devices. This important feature makes memory
design easy and allows a more relaxed approach to interfacing I/O devices.
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The built-in battery-backable time/date clock uses an external 32.768 kHz crystal oscil-
lator. The suggested model circuit for the external oscillator utilizes a single “tiny
logic” active component. The time/date clock can be used to provide periodic interrupts
every 488 µs. Typical battery current consumption is about 3 µA.
lator. The suggested model circuit for the external oscillator utilizes a single “tiny
logic” active component. The time/date clock can be used to provide periodic interrupts
every 488 µs. Typical battery current consumption is about 3 µA.
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Numerous timers and counters can be used to generate interrupts, baud rate clocks, and
timing for pulse generation.
timing for pulse generation.
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Two input-capture channels can be used to measure the width of pulses or to record the
times at which a series of events take place. Each capture channel has a 16-bit counter
and can take input from one or two pins selected from any of 16 pins.
times at which a series of events take place. Each capture channel has a 16-bit counter
and can take input from one or two pins selected from any of 16 pins.
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Two quadrature decoder units accept input from incremental optical shaft encoders.
These units can be used to track the motion of a rotating shaft or similar device.
These units can be used to track the motion of a rotating shaft or similar device.