Philips PTN3501 Manuale Utente

Philips Semiconductors

Product specification

PTN3501

Maintenance and control device

2001 Jan 17

11

C-bus timing (see Figure 19; Note 1)

f

SCL

SCL clock frequency

–

–

400

kHz

t

SW

tolerable spike width on bus

–

–

50

ns

t

BUF

bus free time

1.3

–

–

µ

s

t

SU;STA

START condition set–up time

0.6

–

–

µ

s

t

HD;STA

START condition hold time

0.6

–

–

µ

s

t

r

SCL and SDA rise time

–

–

0.3

µ

s

t

f

SCL and SDA fall time

–

–

0.3

µ

s

t

SU;DAT

data set–up time

250

–

–

ns

t

HD;DAT

data hold time

0

–

–

ns

t

VD;DAT

SCL LOW to data out valid

–

–

1.0

µ

s

t

SU;STO

STOP condition set–up time

0.6

–

–

µ

s

NOTE:
1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to V

IL

 and V

IH

 with an input

voltage swing of V

SS 

to V

DD

.

handbook, full pagewidth

SCL

SDA

MBD820

BIT 0

LSB

(R/W)

t

HD;STA

t

SU;DAT

t

HD;DAT

t

VD;DAT

t

SU;STO

t

f

r

t

t

BUF

t

SU;STA

1 / f

SCL

START

CONDITION

(S)

BIT 7

MSB

(A7)

BIT 6

(A6)

ACKNOWLEDGE

(A)

STOP

CONDITION

(P)

SW00561

PROTOCOL