Intel 253668-032US Manuale Utente
11-26 Vol. 3
MEMORY CACHE CONTROL
The CLFLUSH instruction allow selected cache lines to be flushed from memory. This
instruction give a program the ability to explicitly free up cache space, when it is
known that cached section of system memory will not be accessed in the near future.
The non-temporal move instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and
MOVNTPD) allow data to be moved from the processor’s registers directly into
system memory without being also written into the L1, L2, and/or L3 caches. These
instructions can be used to prevent cache pollution when operating on data that is
going to be modified only once before being stored back into system memory. These
instructions operate on data in the general-purpose, MMX, and XMM registers.
instruction give a program the ability to explicitly free up cache space, when it is
known that cached section of system memory will not be accessed in the near future.
The non-temporal move instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and
MOVNTPD) allow data to be moved from the processor’s registers directly into
system memory without being also written into the L1, L2, and/or L3 caches. These
instructions can be used to prevent cache pollution when operating on data that is
going to be modified only once before being stored back into system memory. These
instructions operate on data in the general-purpose, MMX, and XMM registers.
11.5.6
L1 Data Cache Context Mode
L1 data cache context mode is a feature of processors based on the Intel NetBurst
microarchitecture that support Intel Hyper-Threading Technology. When
CPUID.1:ECX[bit 10] = 1, the processor supports setting L1 data cache context
mode using the L1 data cache context mode flag ( IA32_MISC_ENABLE[bit 24] ).
Selectable modes are adaptive mode (default) and shared mode.
The BIOS is responsible for configuring the L1 data cache context mode.
microarchitecture that support Intel Hyper-Threading Technology. When
CPUID.1:ECX[bit 10] = 1, the processor supports setting L1 data cache context
mode using the L1 data cache context mode flag ( IA32_MISC_ENABLE[bit 24] ).
Selectable modes are adaptive mode (default) and shared mode.
The BIOS is responsible for configuring the L1 data cache context mode.
11.5.6.1 Adaptive Mode
Adaptive mode facilitates L1 data cache sharing between logical processors. When
running in adaptive mode, the L1 data cache is shared across logical processors in
the same core if:
running in adaptive mode, the L1 data cache is shared across logical processors in
the same core if:
•
CR3 control registers for logical processors sharing the cache are identical.
•
The same paging mode is used by logical processors sharing the cache.
In this situation, the entire L1 data cache is available to each logical processor
(instead of being competitively shared).
If CR3 values are different for the logical processors sharing an L1 data cache or the
logical processors use different paging modes, processors compete for cache
resources. This reduces the effective size of the cache for each logical processor.
Aliasing of the cache is not allowed (which prevents data thrashing).
(instead of being competitively shared).
If CR3 values are different for the logical processors sharing an L1 data cache or the
logical processors use different paging modes, processors compete for cache
resources. This reduces the effective size of the cache for each logical processor.
Aliasing of the cache is not allowed (which prevents data thrashing).
11.5.6.2 Shared Mode
In shared mode, the L1 data cache is competitively shared between logical proces-
sors. This is true even if the logical processors use identical CR3 registers and paging
modes.
In shared mode, linear addresses in the L1 data cache can be aliased, meaning that
one linear address in the cache can point to different physical locations. The mecha-
nism for resolving aliasing can lead to thrashing. For this reason,
IA32_MISC_ENABLE[bit 24] = 0 is the preferred configuration for processors based
sors. This is true even if the logical processors use identical CR3 registers and paging
modes.
In shared mode, linear addresses in the L1 data cache can be aliased, meaning that
one linear address in the cache can point to different physical locations. The mecha-
nism for resolving aliasing can lead to thrashing. For this reason,
IA32_MISC_ENABLE[bit 24] = 0 is the preferred configuration for processors based