Agilent Technologies FS2100 Manuale Utente
PVALID_L - Parity Valid
True for the cycles in which parity is
being transmitted on the PCI bus.
being transmitted on the PCI bus.
IDLE_L - Idle cycle
True when the bus is IDLE. False when
the bus is busy.
the bus is busy.
DVALID_L - Data Valid
True when data is being transferred on
the PCI bus.
the PCI bus.
WINITI_L - Master Initiated
Wait State
Wait State
True when a wait state is being initiated
by the master
by the master
WTARGET_L - Target
Initiated Wait State
Initiated Wait State
True when a wait state is being initiated
by the target
by the target
RETRY_L - Retry
True when a retry condition has been
detected on the PCI bus
detected on the PCI bus
TABORT_L - Target Abort
True when a Target Abort condition has
been detected on the PCI bus. This
signal is true for one clock bit.
been detected on the PCI bus. This
signal is true for one clock bit.
WNODEV_L - Wait state
caused by no assertion of
DEVSEL#
caused by no assertion of
DEVSEL#
True when a wait state has been
caused by no assertion of DEVSEL#.
caused by no assertion of DEVSEL#.
GNT_L - The Grant signal for
that slot
that slot
In State Mode this signal is latched and
held until end of transaction. Useful as
a store qualifier.
held until end of transaction. Useful as
a store qualifier.
In timing mode the GNT# from the PCI
bus is passed through to the logic
analyzer.
bus is passed through to the logic
analyzer.
L_CMD - The latched
command lines
command lines
The C/BE signals latched during the
command /address phase and held until
end of transaction.
command /address phase and held until
end of transaction.
AVALID_L - Address Valid
True on the first assertion of FRAME#
and the rising edge of the PCI clock.
True for one cycle except on Dual
Address cycles when it is true for two
cycles.
and the rising edge of the PCI clock.
True for one cycle except on Dual
Address cycles when it is true for two
cycles.
The Data Parity
Checking Logic
Checking Logic
Parity checking is only available in STATE Mode and is
controlled by the PARITY ON switch on the front panel. The
parity generation is done by the IDT 162511 latching buffers.
Only data parity is generated and then checked against the data
parity that is transferred on the bus. If they are not the same
then the signal CPERR_L will be asserted on the cycle that the
parity is valid. This signal will remain valid for one clock tic.
controlled by the PARITY ON switch on the front panel. The
parity generation is done by the IDT 162511 latching buffers.
Only data parity is generated and then checked against the data
parity that is transferred on the bus. If they are not the same
then the signal CPERR_L will be asserted on the cycle that the
parity is valid. This signal will remain valid for one clock tic.
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