Intel L5618 AT80614005079AB Manuale Utente

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Intel
®
 Xeon
®
 Processor 5600 Series Datasheet Volume 1
19
Electrical Specifications
Clock multiplying within the processor is provided by the internal phase locked loop 
(PLL), which requires a constant frequency BCLK_DP, BCLK_DN input, with exceptions 
for spread spectrum clocking. DC specifications for the BCLK_DP, BCLK_DN inputs are 
provided in 
 and AC specifications in 
. These specifications must 
be met while also meeting the associated signal quality specifications outlined in 
.
2.1.6
Test Access Port (TAP) Signals
Due to the voltage levels supported by other components in the Test Access Port (TAP) 
logic, it is recommended that the processor(s) be first in the TAP chain and followed by 
any other components within the system. A translation buffer should be used to 
connect to the rest of the chain unless one of the other components is capable of 
accepting an input of the appropriate voltage. Similar considerations must be made for 
TCK, TDO, TMS, and TRST#. Two copies of each signal may be required with each 
driving a different voltage level.
Processor TAP signal DC specifications can be found in 
. AC specifications are 
Note:
While TDI, TMS and TRST# do not include On-Die Termination (ODT), these signals are 
weakly pulled-up via a 1-5 kΩ resistor to V
TT
.
Note:
While TCK does not include ODT, this signal is weakly pulled-down via a
1-5 kΩ resistor to V
SS
.
2.1.7
Power / Other Signals
Processors also include various other signals including power/ground, sense points, and 
analog inputs. Details can be found in 
 outlines the required voltage supplies necessary to support Intel Xeon 
processor 5600 series.
Note:
1.
Refer to 
 for voltage and current specifications.
2.1.7.1
Power and Ground Lands
For clean on-chip power distribution, processors include lands for all required voltage 
supplies. These include:
Table 2-1.  Processor Power Supply Voltages
1
Power Rail
Nominal Voltage
Notes
V
CC
Se
Each processor includes a dedicated VR11.1 regulator.
V
CCPLL
1.80 V
Each processor includes dedicated V
CCPLL 
and PLL circuits.
V
DDQ
1.50 V
1.35 V
Each processor and DDR3 / DDR3L stack shares a dedicated voltage 
regulator. It is expected that regulators will support both 1.50 and 
1.35 V.
V
TTA
, V
TTD
See 
Each processor includes a dedicated VR11.0 regulator.
V
TT 
= V
TTA
 + V
TTD
; P1V1_Vtt is VID[4:2] controlled, 
VID range is 1.025-1.2000 V; 20 mV offset (see 
); V
TT
 
represents a 
typical
 voltage. V
TT_MIN
 and V
TT_MAX
 loadlines represent a 
31.5 mV offset from V
TT
 (typ).