Kingston Technology 2GB(2 x 1024MB), 400MHZ, DDR, NON-ECC, CL2, 184-Pin DIMM KHX3200ULK2/2G Scheda Tecnica
Codici prodotto
KHX3200ULK2/2G
Memory Module Specification
Document No. 4804408-001.A00
04/12/06
KHX3200ULK2/2G
2GB (1GB 128M x 64-Bit x 2 pcs.)
PC3200 CL2 184-Pin DIMM Kit
KEYED
Page 1
DESCRIPTION:
Kingston's KHX3200ULK2/2G is a kit of two 128M x 64-bit 1GB (1024MB) DDR400 SDRAM (Synchronous
DRAM) CL2 memory modules. Total kit capacity is 2GB (2048MB). Each module pair has been tested to run
at DDR1 400MHz at low latency timing of 2-2-2-5 at 2.7V. The SPD is programmed to JEDEC standard latency
400Mhz timing of 3-3-3-8 at 2.6V.The components on each module include sixteen 64M x 8-bit (16M x 8-bit
x 4 Bank) DDR400 SDRAM in TSOP packages. Each 184-pin DIMM uses gold contact fingers and requires
+2.6V. The electrical and mechanical specifications are as follows:
DRAM) CL2 memory modules. Total kit capacity is 2GB (2048MB). Each module pair has been tested to run
at DDR1 400MHz at low latency timing of 2-2-2-5 at 2.7V. The SPD is programmed to JEDEC standard latency
400Mhz timing of 3-3-3-8 at 2.6V.The components on each module include sixteen 64M x 8-bit (16M x 8-bit
x 4 Bank) DDR400 SDRAM in TSOP packages. Each 184-pin DIMM uses gold contact fingers and requires
+2.6V. The electrical and mechanical specifications are as follows:
FEATURES:
Power supply : Vdd: 2.6V ± 0.2V, Vddq: 2.6V ± 0.2V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 2 (clock)
Programmable Burst length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Timing Reference: 3-3-3-8 at +2.6V / 2-2-2-5 at +2.7V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
Serial presence detect with EEPROM
High Performance Heat Spreader
PCB : Height 1.250” (34.75mm), double sided component
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 2 (clock)
Programmable Burst length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Timing Reference: 3-3-3-8 at +2.6V / 2-2-2-5 at +2.7V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
Serial presence detect with EEPROM
High Performance Heat Spreader
PCB : Height 1.250” (34.75mm), double sided component
PERFORMANCE:
Clock Cycle Time (tCK)
5ns (min.) / 10ns (max.)
Row Cycle Time (tRC)
55ns (min.)
Refresh Row Cycle Time (tRFC) 65ns (min.)
Row Active Time (tRAS)
Row Active Time (tRAS)
40ns (min.) / 100,000ns (max.)
Power
4.125 W (operating per module)
UL Rating
94 V - 0
Operating Temperature
0
o
C to 70
o
C
Storage Temperature
-55
o
C to +150
o
C
T E C H N O L O G Y