Samsung M395T5160QZ4 M395T5160QZ4-CF760 Manuale Utente
Codici prodotto
M395T5160QZ4-CF760
Rev. 1.4 May 2009
FBDIMM
DDR2 SDRAM
5 of 42
2.0 FBDIMM Generals
2.1 FBDIMM Operation Overview
FB-DIMM (Fully Buffered Dual in Line Memory Module) is designed for the applications which require higher data transfer bandwidth and
scalable memory capacity. The memory slot access rate per channel decreases as the memory bus speed increases, resulting in limited
density build-up as channel speeds increase with memory system having the stub-bus architecture. FB-DIMM solution is intended to
eliminate this stub-bus channel bottleneck by using point-to-point links that enable multiple memory modules to be connected serially to
a given channel.
scalable memory capacity. The memory slot access rate per channel decreases as the memory bus speed increases, resulting in limited
density build-up as channel speeds increase with memory system having the stub-bus architecture. FB-DIMM solution is intended to
eliminate this stub-bus channel bottleneck by using point-to-point links that enable multiple memory modules to be connected serially to
a given channel.
Memory system architecture perspective, FB-DIMM is fully differentiated from Registered DIMM and Unbuffered DIMM. A lot of new
technologies are integrated into this solution in order to achieve this scalable higher speed memory solution. Serial link interface with
packet data format and dedicated read/write paths are key attribute in FB-DIMM protocol. Point to Point interconnect with fully differential
signaling and de-emphasis scheme are key attribute in FBD channel link. Clock recovery by using data stream is key attribute in FBD
clocking. FB-DIMM supports both clock resync and resampling mode options. CRC (Cyclic Redundancy Check) bits are transferred with
data stream for reliability at high speed data transaction. Failover mechanism supports system running with dynamic IO failure. Finally all
FB-DIMM is connected in daisy chain manner. Thus, every interconnection between AMB (advanced memory buffer) to AMB, AMB to
Host and AMB to DRAM, is point to point interconnection which allows higher data transfer bandwidth.
technologies are integrated into this solution in order to achieve this scalable higher speed memory solution. Serial link interface with
packet data format and dedicated read/write paths are key attribute in FB-DIMM protocol. Point to Point interconnect with fully differential
signaling and de-emphasis scheme are key attribute in FBD channel link. Clock recovery by using data stream is key attribute in FBD
clocking. FB-DIMM supports both clock resync and resampling mode options. CRC (Cyclic Redundancy Check) bits are transferred with
data stream for reliability at high speed data transaction. Failover mechanism supports system running with dynamic IO failure. Finally all
FB-DIMM is connected in daisy chain manner. Thus, every interconnection between AMB (advanced memory buffer) to AMB, AMB to
Host and AMB to DRAM, is point to point interconnection which allows higher data transfer bandwidth.
Figure 1 shows a lot of new technologies integrated with FBD solution.
Figure 1. FBDIMM Memory system Overview
Host
DRAM
DRAM
AMB
DQs ADDR
CMD
CLK
Tx
Tx
Rx
Rx
Clk_Ref
P2P Interconnect
- LVDS
- De-Emphasis
Reliability
- CRC fail-over
Clock Recovery
Two unidirectional links
- Northbound
- Southbound
Protocol Packet
ADDR.CMD, DATA
SB (ADDR, CMD, Wdata)
NB(Rdata)
DRAM
DRAM
AMB
Tx
Tx
Rx
Rx
Clock
DQs
ADDR
CMD
CLK
FIFO
Buffer
Daisy Chain
Connection
Upto 8 AMB
DIMM Topology
Fly-by CLK, CMD