Intel 2 Duo L7300 LE80537LG0174M Manuale Utente
Codici prodotto
LE80537LG0174M
Datasheet
9
Introduction
1.1
Terminology
Term
Definition
#
A “#” symbol after a signal name refers to an active low signal, indicating a
signal is in the active state when driven to a low level. For example, when
RESET# is low, a reset has been requested. Conversely, when NMI is high,
a nonmaskable interrupt has occurred. In the case of signals where the
name does not imply an active state but describes part of a binary
sequence (such as address or data), the “#” symbol implies that the signal
is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and XXXX
means that the specification or value is yet to be determined.
signal is in the active state when driven to a low level. For example, when
RESET# is low, a reset has been requested. Conversely, when NMI is high,
a nonmaskable interrupt has occurred. In the case of signals where the
name does not imply an active state but describes part of a binary
sequence (such as address or data), the “#” symbol implies that the signal
is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and XXXX
means that the specification or value is yet to be determined.
AGTL+
Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+
signaling technology on some Intel processors.
Front Side Bus
(FSB)
(FSB)
Refers to the interface between the processor and system core logic (also
known as the chipset components).
known as the chipset components).
Intel®
Virtualization
Technology
Virtualization
Technology
Processor virtualization which when used in conjunction with Virtual
Machine Monitor software enables multiple, robust independent software
environments inside a single platform.
Processor Core
Processor core die with integrated L1 and L2 cache. All AC timing and
signal integrity specifications are at the pads of the processor core.
signal integrity specifications are at the pads of the processor core.
Storage
Conditions
Conditions
Refers to a non-operational state. The processor may be installed in a
platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased or receive any
clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device
removed from packaging material) the processor must be handled in
accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
V
CC
The processor core power supply
V
SS
The processor ground reference