takeMS DDR2 512MB, 667 MHz BD512TEC910/A Scheda Tecnica
Codici prodotto
BD512TEC910/A
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General Description
These Memory devices are JEDEC standard unbuffered DIMM modules, based on CMOS
DDR2 SDRAM technology,and are available in 64Mx64 (512MB DDR2 533 and DDR2 667).
These devices consist of 8 CMOS DDR2 SDRAMs in FBGA packages on a 240-pin glass
epoxy substrate.The memory array is designed with Double Data Rate (DDR2) Synchronous
DRAMs for unbuffered applications.
The pipelined, multibanked architecture of DDR2 SDRAMs allows for concurrent operation,
thereby providing high, effective bandwidth. Decoupling capacitors are mounted on the PCB
board in parallel for each DDR2 SDRAM, which provides proper voltage supply impedance
over the whole frequency range of operations, in accordance with JEDEC specifications.
These modules feature Serial Presence Detect (SPD) based on a serial EEPROM device,
using the 2-pin I
2
C protocol.
The first 128 bytes are programmed with configuration data.
Features
• 240-pin Unbuffered 8-Byte ECC DDR2 SDRAM
Memory Module for PC and Workstation main
memory applications
• Dual rank organization 64Mx64
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• V
Features
• 240-pin Unbuffered 8-Byte ECC DDR2 SDRAM
Memory Module for PC and Workstation main
memory applications
• Dual rank organization 64Mx64
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• V
DD
= +1.8V ± 0.1V, V
DD
Q = +1.8V ± 0.1V
• 4-bit prefetch architecture
• Differential data strobe (DQS, DQS#) option
• Differential clock inputs (CK, CK#)
• Programmable CAS Latencies (3, 4, and 5), Burst
Length (4 and 8)
• Posted CAS# additive latency (AL): 0, 1, 2, 3 and 4
• Auto Refresh (CBR) and Self Refresh Mode
• Off-Chip Driver (OCD) Impedance Adjustment
• On-Die Termination (ODT) supports termination
values of 50, 75, and 150 ohms
• Serial Presence Detect (SPD) with EEPROM
• Module layout is based on JEDEC standard routing
guidelines
• Impedance controlled 6-layer PCB Technology
• DQS edge-aligned with data for READs
• DQS center-aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• JEDEC standard form factor (133.35 mm x 30.0 mm)
• Operating Temperature 0°C ~ 95°C
• Differential data strobe (DQS, DQS#) option
• Differential clock inputs (CK, CK#)
• Programmable CAS Latencies (3, 4, and 5), Burst
Length (4 and 8)
• Posted CAS# additive latency (AL): 0, 1, 2, 3 and 4
• Auto Refresh (CBR) and Self Refresh Mode
• Off-Chip Driver (OCD) Impedance Adjustment
• On-Die Termination (ODT) supports termination
values of 50, 75, and 150 ohms
• Serial Presence Detect (SPD) with EEPROM
• Module layout is based on JEDEC standard routing
guidelines
• Impedance controlled 6-layer PCB Technology
• DQS edge-aligned with data for READs
• DQS center-aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• JEDEC standard form factor (133.35 mm x 30.0 mm)
• Operating Temperature 0°C ~ 95°C
Address Table
Refresh Count
8K
Row Addressing
16K (A0 ~ A13)
Device Bank Addressing
4 (BA0, BA1)
Device Configuration
512Mbit (64Mx8)
Column Addressing
1K (A0 ~ A9)
Module Rank Addressing
1 (S0#,)