Toshiba Xeon 2.8GHz UPG3843W Manuale Utente

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UPG3843W
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Intel® Xeon™ Processor with 512 KB L2 Cache
100
  Datasheet
7.2.2
AutoHALT Powerdown State—State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The
processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#,
LINT[1:0] (NMI, INTR), or an interrupt delivered over the front side bus. RESET# will cause the
processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual,
Volume III: System Programmer's Guide
 for more information.
The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.
When the system deasserts the STPCLK# interrupt, the processor will return execution to the
HALT state.
Figure 41. Stop Clock State Machine
2. Auto HALT Power Down State
BCLK running
Snoops and interrupts allowed
1. Normal State
Normal execution
4. HALT/Grant Snoop State
BCLK running
Service snoops to caches
3. Stop Grant State
BCLK running
Snoops and interrupts allowed
5. Sleep State
BCLK running
No snoops or interrupts
allowed
HALT Instruction and
HALT Bus Cycle Generated
Snoop
Event
Occurs
Snoop
Event
Serviced
INIT#, BINIT#, INTR, NMI,
SMI#, RESET#
STPCLK#
Asserted
STPCLK#
De-asserted
ST
PC
LK#
 As
sert
ed
ST
PC
LK
# D
e-a
sse
rted
SLP#
Asserted
SLP#
De-asserted
Snoop Event Occurs
Snoop Event Serviced
.