Toshiba Xeon 2.8GHz UPG3843W Manuale Utente
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UPG3843W
Intel® Xeon™ Processor with 512 KB L2 Cache
128
Datasheet
9.0
Debug Tools Specifications
The Debug Port design information has been moved. This includes all information necessary to
develop a Debug Port on this platform, including electrical specifications, mechanical
requirements, and all In-Target Probe (ITP) signal layout guidelines. Please reference the ITP700
Debug Port Design Guide for the design of your platform.
develop a Debug Port on this platform, including electrical specifications, mechanical
requirements, and all In-Target Probe (ITP) signal layout guidelines. Please reference the ITP700
Debug Port Design Guide for the design of your platform.
9.1
Logic Analyzer Interface (LAI)
Intel® is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for
use in debugging systems. Tektronix* and Agilent* should be contacted to get specific information
about their logic analyzer interfaces. The following information is general in nature. Specific
information must be obtained from the logic analyzer vendor.
use in debugging systems. Tektronix* and Agilent* should be contacted to get specific information
about their logic analyzer interfaces. The following information is general in nature. Specific
information must be obtained from the logic analyzer vendor.
Due to the complexity of systems, the LAI is critical in providing the ability to probe and capture
front side bus signals. There are two sets of considerations to keep in mind when designing a
system that can make use of an LAI: mechanical and electrical.
front side bus signals. There are two sets of considerations to keep in mind when designing a
system that can make use of an LAI: mechanical and electrical.
9.1.1
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI pins plug into the
socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI
egresses the system to allow an electrical connection between the processor and a logic analyzer.
The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable
egress restrictions, should be obtained from the logic analyzer vendor. System designers must
make sure that the keepout volume remains unobstructed inside the system. Note that it is possible
that the keepout volume reserved for the LAI may differ from the space normally occupied by the
processor heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as
part of the LAI.
socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI
egresses the system to allow an electrical connection between the processor and a logic analyzer.
The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable
egress restrictions, should be obtained from the logic analyzer vendor. System designers must
make sure that the keepout volume remains unobstructed inside the system. Note that it is possible
that the keepout volume reserved for the LAI may differ from the space normally occupied by the
processor heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as
part of the LAI.
9.1.2
Electrical Considerations
The LAI will also affect the electrical performance of the front side bus; therefore, it is critical to
obtain electrical load models from each of the logic analyzers to be able to run system level
simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for
electrical specifications and load models for the LAI solution they provide.
obtain electrical load models from each of the logic analyzers to be able to run system level
simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for
electrical specifications and load models for the LAI solution they provide.