Toshiba Xeon 2.8GHz UPG3843W Manuale Utente

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1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source

synchronous data signals are referenced to the falling edge of their associated data strobe. Source
synchronous address signals are referenced to the rising and falling edge of their associated address strobe.
All source synchronous AGTL+ signal timings are referenced at GTLREF at the processor core.

4. Unless otherwise noted, these specifications apply to both data and address timings.
5. Valid delay timings for these signals are specified into the test circuit described in 

 and with GTLREF

at 2/3 * V

CC

 

± 2%.

6. Specification is for a minimum swing defined between AGTL+ V

IL_MAX

 to V

IH_MIN

. This assumes an edge rate

of

 

0.3 V/nS to 4.0 V/nS.

7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each

respective strobe.

8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the

appropriate platform design guidelines for more information on the definitions and use of these specifications.

9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the

appropriate platform design guidelines for more information on the definitions and use of these specifications.

10.The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 nS) after the falling edge of

ADSTB#.

11. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.

12.The second data strobe (the falling edge of DSTBn#) must come approximately 1/4 BCLK period (2.5 nS)

after the first falling edge of DSTBp#. The third data strobe (the falling edge of DSTBp#) must come
approximately 2/4 BCLK period (5 nS) after the first falling edge of DSTBp#. The last data strobe (the falling
edge of DSTBn#) must come approximately 3/4 BCLK period (7.5 nS) after the first falling edge of DSTBp#.

13.This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.
14.This specification reflects a typical value, not a minimum or maximum..

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing

Voltage (V

CROSS

). All Asynchronous GTL+ signal timings are referenced at GTLREF.

3. These signals may be driven asynchronously.
4. Refer to 

 for additional timing requirements for entering and leaving low power states.

5. Refer to the PWRGOOD signal definition in 

 for more detail information on behavior of the signal.

6. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the

assertion of PROCHOT# for the processor to complete current instruction execution

.

T29: T

FDSS

: First Data Strobe to Subsequent 

Strobes

n/4

BCLKs

1, 2, 3, 4, 

11, 12, 

14

T30: Data Strobe ‘n’ (DSTBN#) Output Valid Delay 

8.80

10.20

nS

 1, 2, 3, 

4, 13

T31: Address Strobe Output Valid Delay

2.27

4.23

nS

 1, 2, 3, 4

T35: Async GTL+ input pulse width

2

N/A

BCLKs

1, 2, 3, 4

T36: PWRGOOD to RESET# de-assertion time

1

10

mS

1, 2, 3, 4

T37: PWRGOOD inactive pulse width

10

N/A

BCLKs

1, 2, 3, 4, 

5

T38: PROCHOT# pulse width

500

µS

1, 2, 3, 4, 

6

T39: THERMTRIP# to Vcc Removal

0.5

S