Toshiba Xeon 2.8GHz UPG3843W Manuale Utente
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UPG3843W
Intel® Xeon™ Processor with 512 KB L2 Cache
40
Datasheet
Figure 11. Front Side Bus Source Synchronous 4X (Data) Timing Waveform
BCLK0
BCLK1
DSTBp# (@ driver)
DSTBn# (@ driver)
D# (@ driver)
D# (@ receiver)
DSTBn# (@ receiver)
DSTBp# (@ receiver)
T0
T1
T2
1/4
BCLK
1/2
BCLK
3/4
BCLK
T
A
T
A
T
B
T
C
T
E
T
E
T
G
T
G
T
D
T
A
= T21: Source Sync. Data Output Valid Delay Before Data Strobe
T
B
= T22: Source Sync. Data Output Valid Delay After Data Strobe
T
C
= T27: Source Sync. Setup Time to BCLK
T
D
= T30: Source Sync. Data Strobe 'N' (DSTBN#) Output Valid Delay
T
E
= T25: Source Sync. Input Setup Time
T
G
= T26: Source Sync. Input Hold Time
T
H
= T29: First Data Strobe to Subsequent Strobes
T
J
= T20: Source Sync. Data Output Valid Delay
T
J
T
H