Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Scheda Tecnica
Codici prodotto
AT91SAM9N12-EK
Programmer’s Model
2-18
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
Figure 2-7 Register c3 format
Each two-bit field defines the access permissions for one of the 16 domains (D15-D0)
(see Table 2-14).
(see Table 2-14).
Reading from c3 returns the value of the Domain Access Control Register.
Writing to c3 writes the value of the Domain Access Control Register.
You can use the following instructions to access the Domain Access Control Register:
MRC p15, 0, <Rd>, c3, c0, 0 ; read domain access permissions
MCR p15, 0, <Rd>, c3, c0, 0 ; write domain access permissions
MCR p15, 0, <Rd>, c3, c0, 0 ; write domain access permissions
2.3.5
Register c4
Accessing (reading or writing) this register causes Unpredictable behavior.
2.3.6
Fault Status Registers c5
Register c5 accesses the Fault Status Registers (FSRs). The FSRs contain the source of
the last instruction or data fault. The instruction-side FSR is intended for debug
purposes only. The FSR is updated for alignment faults, and external aborts that occur
while the MMU is disabled.
the last instruction or data fault. The instruction-side FSR is intended for debug
purposes only. The FSR is updated for alignment faults, and external aborts that occur
while the MMU is disabled.
D15
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 2-14 Domain access control defines
Value
Meaning
Description
00
No access
Any access generates a domain fault.
01
Client
Accesses are checked against the access permission bits in
the section or page descriptor.
the section or page descriptor.
10
Reserved
Reserved. Currently behaves like the no access mode.
11
Manager
Accesses are not checked against the access permission
bits so a permission fault cannot be generated.
bits so a permission fault cannot be generated.