Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Scheda Tecnica
Codici prodotto
AT91SAM9N12-EK
101
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
12.2.4.5 Hardware and Software Constraints
The NVM drivers use several PIOs in peripheral mode to communicate with external memory devices. Care must be
taken when these PIOs are used by the application. The devices connected could be unintentionally driven at boot time,
and electrical conflicts between output pins used by the NVM drivers and the connected devices may occur.
taken when these PIOs are used by the application. The devices connected could be unintentionally driven at boot time,
and electrical conflicts between output pins used by the NVM drivers and the connected devices may occur.
To assure correct functionality, it is recommended to plug in critical devices to other pins not used by NVM.
contains a list of pins that are driven during the boot program execution. These pins are driven during the boot
sequence for a period of less than 1 second if no correct boot program is found.
Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program
are set to their reset state.
are set to their reset state.
Table 12-4. PIO Driven during Boot Program Execution
NVM Bootloader
Peripheral
Pin
PIO Line
NAND
EBI CS3 SMC
NANDOE
PIOD0
EBI CS3 SMC
NANDWE
PIOD1
EBI CS3 SMC
NANDCS
PIOD4
EBI CS3 SMC
NAND ALE
A21
EBI CS3 SMC
NAND CLE
A22
EBI CS3 SMC
Cmd/Addr/Data
D[16:0]
SD Card
MCI0
MCI0_CK
PIOA17
MCI0
MCI0_D0
PIOA15
MCI0
MCI0_D1
PIOA18
MCI0
MCI0_D2
PIOA19
MCI0
MCI0_D3
PIOA20
SPI Flash
SPI0
MOSI PIOA10
SPI0
MISO
PIOA11
SPI0
SPCK
PIOA13
SPI0
NPCS0
PIOA14
SPI0
NPCS1
PIOA7
TWI0 EEPROM
TWI0
TWD0
PIOA30
TWI0
TWCK0
PIOA31
SAM-BA Monitor
DBGU
DRXD
PIOA9
DBGU
DTXD
PIOA10