Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Scheda Tecnica

1025

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

Let’s assume the message is received through a serial to parallel communication channel, the first received character is
0xca and stored at first memory location (initial offset), second octet being 0xfe is stored at initial offset + 1. 

When reading on a 32-bit Little Endian system bus, the first word read back from system memory is 0x_dede_feca.

When the SHA_ODATAxR registers are read, the hash result is organized in Little Endian format, allowing system
memory storage in the same format as the message.

Taking an example from the FIPS 180-2 specification Appendix B.1, the endianism conversion can be observed.

For this example, the 512-bit message is:

0x6162638000000000000000000000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000018

and the expected SHA-256 result is:

0xba7816bf_8f01cfea_414140de_5dae2223_b00361a3_96177a9c_b410ff61_f20015ad

If the message has not already been stored in the system memory, the first step is to convert the input message to Little
Endian before writing to the SHA_IDATAxR registers. This would result in a write of:

SHA_IDATA0R = 0x80636261...... SHA_IDATA15R = 0x18000000

The data in the output message digest registers, SHA_ODATAxR, contain SHA_ODATAxR = 0xbf1678ba...
SHA_ODATA7R = 0xad1500f2 which is the Little Endian format of 0xba7816bf,..., 0xf20015ad.

Reading SHA_ODATA0R to SHA_ODATA1R and storing into a Little Endian memory system forces hash results to be
stored in the same format as the message.

When the output message is read, the user can convert back to Big Endian for a resulting message value of:

0xba7816bf_8f01cfea_414140de_5dae2223_b00361a3_96177a9c_b410ff61_f20015ad

When an unspecified register access occurs, the URAD bit in the Interrupt Status Register (SHA_ISR) raises. Its source
is then reported in the Unspecified Register Access Type field (URAT). Only the last unspecified register access is
available through the URAT field.

Several kinds of unspecified register accesses can occur:



Input Data Register written during the data processing in DMA  mode



Output Data Register read during the data processing



Mode Register written during the data processing



Write-only register read access

The URAD bit and the URAT field can only be reset by the SWRST bit in the SHA_CR control register.