Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Scheda Tecnica

Codici prodotto

AT91SAM9N12-EK

311

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

27.4

I/O Lines Description

The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the
moment.

Table 27-2 on page 311

details the connections between the two Memory Controllers and the EBI pins.

Table 27-1. EBI I/O Lines Description

Name

Function

Type

Active Level

EBI

EBI_D0 - EBI_D31

Data Bus

I/O

EBI_A0 - EBI_A25

Address Bus

Output

EBI_NWAIT

External Wait Signal

Input

Low

SMC

EBI_NCS0 - EBI_NCS5

Chip Select Lines

Output

Low

EBI_NWR0 - EBI_NWR3

Write Signals

Output

Low

EBI_NRD

Read Signal

Output

Low

EBI_NWE

Write Enable

Output

Low

EBI_NBS0 - EBI_NBS3

Byte Mask Signals

Output

Low

EBI for NAND Flash Support

EBI_NANDCS

NAND Flash Chip Select Line

Output

Low

EBI_NANDOE

NAND Flash Output Enable

Output

Low

EBI_NANDWE

NAND Flash Write Enable

Output

Low

DDR2/SDRAM Controller

EBI_SDCK, EBI_SDCK#

DDR2/SDRAM Differential Clock

Output

EBI_SDCKE

DDR2/SDRAM Clock Enable

Output

High

EBI_SDCS

DDR2/SDRAM Controller Chip Select Line

Output

Low

EBI_BA0 - 2

Bank Select

Output

EBI_SDWE

DDR2/SDRAM Write Enable

Output

Low

EBI_RAS - EBI_CAS

Row and Column Signal

Output

Low

EBI_SDA10

SDRAM Address 10 Line

Output

Table 27-2. EBI Pins and Memory Controllers I/O Lines Connections

EBIx Pins

SDRAM I/O Lines

SMC I/O Lines

EBI_NWR1/NBS1/CFIOR

NBS1

NWR1

EBI_A0/NBS0

Not Supported

SMC_A0

EBI_A1/NBS2/NWR2

Not Supported

SMC_A1

EBI_A[11:2]

SDRAMC_A[9:0]

SMC_A[11:2]

EBI_SDA10

SDRAMC_A10

Not Supported

EBI_A12

Not Supported

SMC_A12

EBI_A[14:13]

SDRAMC_A[12:11]

SMC_A[14:13]

EBI_A[25:15]

Not Supported

SMC_A[25:15]

EBI_D[31:0]

D[31:0]