Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Scheda Tecnica
Codici prodotto
AT91SAM9N12-EK
441
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
31.6.2 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Eight Banks
31.6.3 SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width
Table 31-8. Interleaved Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Row[13:0]
Bk[1:0]
Column[8:0]
M0
Row[13:0]
Bk[1:0]
Column[9:0]
M0
Row[13:0]
Bk[1:0]
Column[10:0]
M0
Table 31-9. Linear Mapping for SDRAM Configuration: 8K Rows, 1024 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bk[2:0]
Row[12:0]
Column[9:0]
M0
Table 31-10. Linear Mapping for SDRAM Configuration: 16K Rows, 1024 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bk[2:0]
Row[13:0]
Column[9:0]
M0
Table 31-11. Interleaved Mapping for SDRAM Configuration: 8K Rows, 1024 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Row[12:0]
Bk[2:0]
Column[9:0]
M0
Table 31-12. Interleaved Mapping for SDRAM Configuration: 16K Rows, 1024 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Row[12:0]
Bk[2:0]
Column[9:0]
M0
Table 31-13. SDR-SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bk[1:0]
Row[10:0]
Column[7:0]
M[1:0]
Bk[1:0]
Row[10:0]
Column[8:0]
M[1:0]
Bk[1:0]
Row[10:0]
Column[9:0]
M[1:0]
Bk[1:0]
Row[10:0]
Column[10:0]
M[1:0]