Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Scheda Tecnica
Codici prodotto
AT91SAM9N12-EK
526
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Figure 33-8. Data IN Transfer for Ping-pong Endpoint
Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for
TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set too long, some
Data IN packets may be NACKed, reducing the bandwidth.
TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set too long, some
Data IN packets may be NACKed, reducing the bandwidth.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
33.6.2.3 Data OUT Transaction
Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data
from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-
pong attributes.
from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-
pong attributes.
Data OUT Transaction Without Ping-pong Attributes
To perform a Data OUT transaction, using a non ping-pong endpoint:
1.
The host generates a Data OUT packet.
2.
This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by
the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by
the USB device and an ACK is automatically carried out to the host.
the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by
the USB device and an ACK is automatically carried out to the host.
3.
The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the end-
point’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set.
point’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set.
4.
The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s
UDP_CSRx register.
UDP_CSRx register.
5.
The microcontroller carries out data received from the endpoint’s memory to its memory. Data received is available
by reading the endpoint’s UDP_FDRx register.
by reading the endpoint’s UDP_FDRx register.
6.
The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the end-
point’s UDP_CSRx register.
point’s UDP_CSRx register.
7.
A new Data OUT packet can be accepted by the USB device.
Data IN
Data IN
Read by USB Device
Read by USB Device
Bank 1
Bank 0
FIFO (DPR)
TXCOMP Flag
(UDP_CSRx)
(UDP_CSRx)
Interrupt Cleared by Firmware
Set by USB
Device
Device
TXPKTRDY Flag
(UDP_MCSRx)
(UDP_MCSRx)
ACK
PID
Data IN
PID
ACK
PID
Set by Firmware,
Data Payload Written in FIFO Bank 1
Data Payload Written in FIFO Bank 1
Cleared by USB Device,
Data Payload Fully Transmitted
Data Payload Fully Transmitted
Data IN
PID
USB Bus
Packets
Packets
Set by USB Device
Set by Firmware,
Data Payload Written in FIFO Bank 0
Data Payload Written in FIFO Bank 0
Written by
FIFO (DPR)
Microcontroller
Written by
Microcontroller
Written by
Microcontroller
Microcontroller
Load Data IN Bank 0
Load Data IN Bank 0
Microcontroller Load Data IN Bank 1
USB Device Send Bank 0
USB Device Send Bank 0
Microcontroller Load Data IN Bank 0
USB Device Send Bank 1
USB Device Send Bank 1
Interrupt Pending