Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Scheda Tecnica
Codici prodotto
AT91SAM9N12-EK
715
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Figure 39-13. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
39.8.6.2 10-bit Slave Addressing
For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave
address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and
IADR[23:16] can be used the same as in 7-bit Slave Addressing.
address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and
IADR[23:16] can be used the same as in 7-bit Slave Addressing.
Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
1.
Program IADRSZ = 1,
2.
Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3.
Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address)
below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal
addresses to access the device.
Figure 39-14. Internal Address Usage
39.8.7 Using the DMA Controller
The use of the DMA significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequence.
39.8.7.1 Data Transmit with the DMA
1.
Initialize the DMA (channels, memory pointers, size -1, etc.).
2.
Configure the master mode (DADR, CKDIV, etc.) or slave mode.
3.
Enable the DMA.
4.
Wait for the DMA BTC flag.
5.
Disable the DMA.
6.
Wait for the TXRDY flag in TWI_SR.
7.
Set the STOP command in TWI_CR.
8.
Write the last character in TWI_THR.
9.
(Optional) Wait for the TXCOMP flag in TWI_SR before disabling the peripheral clock if required.
S
DADR
W
A
IADR(23:16)
A
IADR(15:8)
A
IADR(7:0)
A
S
DADR
W
A
IADR(15:8)
A
IADR(7:0)
A
A
IADR(7:0)
A
S
DADR
W
DATA
NA
P
Sr
DADR
R
A
Sr
DADR
R
A
DATA
NA
P
Sr
DADR
R
A
DATA
NA
P
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
S
T
A
R
T
T
A
R
T
M
S
B
B
Device
Address
0
L
S
B
B
R
/
W
A
C
K
C
K
M
S
B
B
W
R
I
T
E
E
A
C
K
C
K
A
C
K
C
K
L
S
B
B
A
C
K
C
K
FIRST
WORD ADDRESS
SECOND
WORD ADDRESS
DATA
S
T
T
O
P