Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Scheda Tecnica

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The LCD controller consists of logic for transferring LCD image data from an external display buffer to an LCD module.
The LCD has one display input buffer that fetches pixels through the AB master interface and a lookup table to allow
palletized display configurations. The LCD controller is programmable on a per overlay basis, and supports different LCD
resolution, window size, image format and pixel depth.

The LCD is connected to the ARM Advanced High Performance Bus (AHB) as a master for reading pixel data. It also
integrates an APB interface to configure its registers.

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One AHB Master Interface 

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Supports Single Scan Active TFT Display

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Supports 12-, 16-, 18- and 24-bit Output Mode through the Spatial Dithering Unit

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Asynchronous Output Mode Supported

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1, 2, 4, 8 bits per pixel (palletized)

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12, 16, 18, 19, 24, 25 and 32 bits per pixel (non palletized)

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Supports One Base Layer (background)

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Little Endian Memory Organization

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Programmable Timing Engine, with Integer Clock Divider

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Programmable Polarity for Data, Line Synchro and Frame Synchro

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Display Size up to 1280 x 860

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Color Lookup Table with up to 256 entries

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Programmable Negative and Positive Row Striding 

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DMA User interface uses Linked List Structure and Add-to-queue Structure