Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Scheda Tecnica

941

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

The fault protection on a channel is triggered when this channel is enabled and when any one of the faults that are 

enabled for this channel is active. It can be triggered even if the PWM master clock (MCK) is not running but only 

by a fault input that is not glitch filtered.
When the fault protection is triggered on a channel, the fault protection mechanism resets the counter of this 

channel and forces the channel outputs to the values defined by the fields FPVHx and FPVLx in the 

 (PWM_FPV) . The output forcing is made asynchronously to the channel counter.

CAUTION:



To prevent an unexpected activation of the status flag FSy in the PWM_FSR, the FMODy bit can be set to ‘1’ 

only if the FPOLy bit has been previously configured to its final value.



To prevent an unexpected activation of the Fault Protection on the channel x, the bit FPEx[y] can be set to ‘1’ 

only if the FPOLy bit has been previously configured to its final value.

If a comparison unit is enabled (see 

) and if a fault is triggered in the 

channel 0, in this case the comparison cannot match.
As soon as the fault protection is triggered on a channel, an interrupt (different from the interrupt generated at the 

end of the PWM period) can be generated but only if it is enabled and not masked. The interrupt is reset by reading 

the interrupt status register, even if the fault which has caused the trigger of the fault protection is kept active.

Some channels can be linked together as synchronous channels. They have the same source clock, the same 

period, the same alignment and are started together. In this way, their counters are synchronized together. 
The synchronous channels are defined by the SYNCx bits in the 

 

(PWM_SCM). Only one group of synchronous channels is allowed.
When a channel is defined as a synchronous channel, the channel 0 is automatically defined as a synchronous 

channel too, because the channel 0 counter configuration is used by all the synchronous channels.
If a channel x is defined as a synchronous channel, it uses the following configuration fields of the channel 0 

instead of its own:



CPRE0 field in PWM_CMR0 instead of CPREx field in PWM_CMRx (same source clock)



CPRD0 field in PWM_CMR0 instead of CPRDx field in PWM_CMRx (same period)



CALG0 field in PWM_CMR0 instead of CALGx field in PWM_CMRx (same alignment)

Thus writing these fields of a synchronous channel has no effect on the output waveform of this channel (except 

channel 0 of course).
Because counters of synchronous channels must start at the same time, they are all enabled together by enabling 

the channel 0 (by the CHID0 bit in PWM_ENA register). In the same way, they are all disabled together by 

disabling channel 0 (by the CHID0 bit in PWM_DIS register). However, a synchronous channel x different from 

channel 0 can be enabled or disabled independently from others (by the CHIDx bit in PWM_ENA and PWM_DIS 

registers).
Defining a channel as a synchronous channel while it is an asynchronous channel (by writing the bit SYNCx to ‘1’ 

while it was at ‘0’) is allowed only if the channel is disabled at this time (CHIDx = 0 in 

PWM_SR)

. In the same way, 

defining a channel as an asynchronous channel while it is a synchronous channel (by writing the SYNCx bit to ‘0’ 

while it was 1) is allowed only if the channel is disabled at this time.
The field UPDM (Update Mode) in the PWM_SCM register allow to select one of the three methods to update the 

registers of the synchronous channels:



Method 1 (UPDM = 0): The period value, the duty-cycle values and the dead-time values must be written by 

the CPU in their respective update registers (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and 

PWM_DTUPDx).The update is triggered at the next PWM period as soon as the bit UPDULOCK in the