Intel U2500 LE80539UE0092M Manuale Utente
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LE80539UE0092M
Datasheet
25
Electrical Specifications
3.5
Signal Terminations and Unused Pins
All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to V
CC
,
V
SS
, or to any other signal (including each other) can result in component malfunction
processor and the location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if
AGTL+ termination is provided on the processor silicon. Unused active high inputs
should be connected through a resistor to ground (V
SS
). Unused outputs can be left
unconnected.
The TEST1 pin must have a stuffing option connection to V
SS
. The TEST2 pin must have
a 51 Ω ±5%, pull-down resistor to V
SS
.
3.6
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). These signals should be connected to the clock chip and the Mobile Intel
945 Express Chipset family on the platform. The BSEL encoding for BCLK[1:0] is shown
in
:
3.7
FSB Signal Groups
In order to simplify the following discussion, the FSB signals have been combined into
groups by buffer type. AGTL+ input signals have differential input buffers, which use
GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+
Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when
driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
identifies which signals are common clock, source synchronous,
and asynchronous.
Table 3.
BSEL[2:0] Encoding for BCLK Frequency
BSEL[2]
BSEL[1]
BSEL[0]
BCLK
Frequency
L
L
L
RESERVED
L
L
H
133 MHz
L
H
L
RESERVED
L
H
H
166 MHz