Intel 8XC196MH Manuale Utente

8XC196MC, MD, MH USER’S MANUAL

4-18

ldb wsr, #?WSR ;Prolog code for wsr

add var1, var2, var3
;
;
;

ldb wsr, [sp] ;Epilog code for wsr
add sp, #2 ;Epilog code for wsr
ret
end
******************************

The following is an example of a linker invocation to link and locate the modules and to deter-
mine the proper windowing.

RL196 MOD1.OBJ, MOD2.OBJ registers(100h-01ffh) windowsize(32)

The above linker controls tell the linker to use registers 0100–01FFH for windowing and to use
a window size of 32 bytes. (These two controls enable windowing.)

The following is the map listing for the resultant output module (MOD1 by default):

SEGMENT MAP FOR mod1(MOD1):

TYPE    BASE LENGTH ALIGNMENT MODULE NAME
----    ---- ------ --------- -----------
**RESERVED*     0000H 001AH
STACK     001AH 0006H WORD
*** GAP ***     0020H 00E0H
OVRLY     0100H 0006H WORD MOD2
OVRLY     0106H 0006H WORD MOD1
*** GAP ***     010CH 1F74H
CODE    2080H 0011H BYTE MOD2
CODE    2091H 0011H BYTE MOD1
*** GAP ***     20A2H DF5EH

This listing shows the disassembled code: