Manuali utente per AMD 6

Sommario

• AMD Athlon™ Processor Model 6 Revision Guide

  1
• AMD Athlon™ Processor Model 6 Revision Guide

  4
  • Revision Guide Policy

    4
• 1 Product Errata

  5
  • Table 1. CrossReference of Product Revision to Errata

    5
  • Table 2. Cross-Reference of Erratum to Processor Segments

    6
  • 16 INVLPG Instruction Does Not Flush Entire Four-Megabyte Page Properly with Certain Linear Addre...

    7
  • 17 Deadlock May Occur in a Two-Processor System in the Presence of Probe to Memory- Mapped I/O

    8
  • 18 Processor May Issue Non-Connect Bus Cycle After FID Special Cycle

    9
  • 19 Processor Does Not Support Reliable Microcode Patch Mechanism

    10
  • 20 Processor Performance Counters Do Not Count Some x86 Instructions

    11
  • 21 A Speculative SMC Store Followed by an Actual SMC Store May Cause One-Time Stale Execution

    12
  • 22 Real Mode RDPMC with Illegal ECX May Cause Unpredictable Operation

    13
  • 23 Using Task Gates With Breakpoints Enabled May Cause Unexpected Faults

    14
  • 24 Single Step Across I/O SMI Skips One Debug Trap

    15
• 2 Revision Determination

  16
  • Table 3. CPUID Values for the Revisions of the AMD Athlon™ Processor Model 6

    16
• 3 Technical and Documentation Support

  17