Manuale UtenteSommarioList of Figures5List of Tables9Overview131.1 General Description131.2 Features14Architecture Overview172.1 GX1 Module172.1.1 Memory Controller172.1.2 Fast-PCI Bus222.1.3 Display222.2 Video Processor Module222.2.1 GX1 Module Interface222.2.2 Video Input Port222.2.3 Core Logic Module Interface222.2.4 CRT DAC222.3 Core Logic Module222.3.1 Other Core Logic Module Interfaces222.4 SuperI/O Module232.5 Clock, Timers, and Reset Logic232.5.1 Reset Logic232.5.1.1 Power-On Reset232.5.1.2 System Reset23Signal Definitions253.1 Ball Assignments273.2 Strap Options443.3 Multiplexing Configuration453.4 Signal Descriptions493.4.1 System Interface493.4.2 Memory Interface Signals503.4.3 Video Port Interface Signals513.4.4 CRT/TFT Interface Signals523.4.5 TV Interface Signals543.4.6 ACCESS.bus Interface Signals553.4.7 PCI Bus Interface Signals553.4.8 Sub-ISA Interface Signals593.4.9 Low Pin Count (LPC) Bus Interface Signals603.4.10 IDE Interface Signals613.4.11 Universal Serial Bus (USB) Interface Signals623.4.12 Serial Ports (UARTs) Interface Signals623.4.13 Parallel Port Interface Signals633.4.14 Fast Infrared (IR) Port Interface Signals643.4.15 AC97 Audio Interface Signals653.4.16 Power Management Interface Signals653.4.17 GPIO Interface Signals673.4.18 Debug Monitoring Interface Signals683.4.19 JTAG Interface Signals683.4.20 Test and Measurement Interface Signals693.4.21 Power and Ground Connections70General Configuration Block714.1 Configuration Block Addresses714.2 Pin Multiplexing, Interrupt Selection, and Base Address Registers724.3 WATCHDOG794.3.1 Functional Description794.3.1.1 WATCHDOG Timer794.3.2 WATCHDOG Registers804.3.2.1 Usage Hints804.4 High-Resolution Timer814.4.1 Functional Description814.4.2 High-Resolution Timer Registers814.4.2.1 Usage Hints814.5 Clock Generators and PLLs834.5.1 27 MHz Crystal Oscillator844.5.2 GX1 Module Core Clock854.5.3 Internal Fast-PCI Clock854.5.4 SuperI/O Clocks864.5.5 Core Logic Module Clocks864.5.6 Video Processor Clocks864.5.7 Clock Registers87SuperI/O Module895.1 Features905.2 Module Architecture915.3 Configuration Structure / Access925.3.1 Index-Data Register Pair925.3.2 Banked Logical Device Registers925.3.3 Default Configuration Setup935.3.4 Address Decoding935.4 Standard Configuration Registers945.4.1 SIO Control and Configuration Registers975.4.2 Logical Device Control and Configuration985.4.2.1 LDN 00h - Real-Time Clock985.4.2.2 LDN 01h - System Wakeup Control1005.4.2.3 LDN 02h - Infrared Communication Port or Serial Port 31015.4.2.4 LDN 03h and 08h - Serial Ports 1 and 21025.4.2.5 LDN 05h and 06h - ACCESS.bus Ports 1 and 21035.4.2.6 LDN 07h - Parallel Port1045.5 Real-Time Clock (RTC)1055.5.1 Bus Interface1055.5.2 RTC Clock Generation1055.5.2.1 Internal Oscillator1055.5.2.2 External Oscillator1065.5.2.3 Timing Generation1065.5.2.4 Timekeeping1075.5.2.5 Alarms1075.5.2.6 Power Supply1085.5.2.7 System Power States1095.5.2.8 Oscillator Activity1095.5.2.9 Interrupt Handling1105.5.2.10 Battery-Backed RAMs and Registers1105.5.3 RTC Registers1115.5.3.1 Usage Hints1155.5.4 RTC General-Purpose RAM Map1155.6 System Wakeup Control (SWC)1165.6.1 Event Detection1165.6.1.1 Audio Codec Event1165.6.1.2 CEIR Address1165.6.2 SWC Registers1175.7 ACCESS.bus Interface1215.7.1 Data Transactions1215.7.2 Start and Stop Conditions1215.7.3 Acknowledge (ACK) Cycle1225.7.4 Acknowledge After Every Byte Rule1235.7.5 Addressing Transfer Formats1235.7.6 Arbitration on the Bus1235.7.7 Master Mode1235.7.7.1 Master Stop1245.7.8 Slave Mode1255.7.9 Configuration1255.7.10 ACB Registers1265.8 Legacy Functional Blocks1295.8.1 Parallel Port1295.8.1.1 Parallel Port Register and Bit Maps1295.8.2 UART Functionality (SP1 and SP2)1315.8.2.1 UART Mode Register Bank Overview1315.8.2.2 SP1 and SP2 Register and Bit Maps for UART Functionality1315.8.3 IR Communications Port (IRCP) / Serial Port 3 (SP3) Functionality1355.8.3.1 IR/SP3 Mode Register Bank Overview1355.8.3.2 IRCP/SP3 Register and Bit Maps135Core Logic Module1416.1 Feature List1416.2 Module Architecture1426.2.1 Fast-PCI Interface to External PCI Bus1436.2.1.1 Processor Mastered Cycles1436.2.1.2 External PCI Mastered Cycles1436.2.1.3 Core Logic Internal or Sub-ISA Mastered Cycles1436.2.1.4 External PCI Bus1436.2.1.5 Bus Master Request Priority1436.2.2 PSERIAL Interface1436.2.2.1 Video Retrace Interrupt1446.2.3 IDE Controller1446.2.3.1 IDE Configuration Registers1446.2.3.2 PIO Mode1446.2.3.3 Bus Master Mode1456.2.3.4 UltraDMA/33 Mode1466.2.4 Universal Serial Bus1476.2.5 Sub-ISA Bus Interface1476.2.5.1 Sub-ISA Bus Cycles1486.2.5.2 Sub-ISA Support of Delayed PCI Transactions1486.2.5.3 Sub-ISA Bus Data Steering1496.2.5.4 I/O Recovery Delays1496.2.5.5 ISA DMA1506.2.5.6 ROM Interface1516.2.5.7 PCI and Sub-ISA Signal Cycle Multiplexing1516.2.6 AT Compatibility Logic1526.2.6.1 DMA Controller1526.2.6.2 Programmable Interval Timer1546.2.6.3 Programmable Interrupt Controller1556.2.7 I/O Ports 092h and 061h System Control1566.2.7.1 I/O Port 092h System Control1576.2.7.2 I/O Port 061h System Control1576.2.7.3 SMI Generation for NMI1576.2.8 Keyboard Support1576.2.8.1 Fast Keyboard Gate Address 20 and CPU Reset1576.2.9 Power Management Logic1586.2.9.1 CPU States1586.2.9.2 Sleep States1596.2.9.3 Power Planes Control1606.2.9.4 Power Management Events1606.2.9.5 Usage Hints1616.2.10 Power Management Programming1626.2.10.1 APM Support1626.2.10.2 CPU Power Management1626.2.10.3 Peripheral Power Management1646.2.10.4 Power Management Programming Summary1666.2.11 GPIO Interface1676.2.12 Integrated Audio1676.2.12.1 Data Transport Hardware1676.2.12.2 AC97 Codec Interface1706.2.12.3 VSA Technology Support Hardware1716.2.12.4 IRQ Configuration Registers1736.2.12.5 LPC Interface1736.2.12.6 LPC Interface Signal Definitions1746.2.12.7 Cycle Types1746.2.12.8 LPC Interface Support1746.3 Register Descriptions1756.3.1 PCI Configuration Space and Access Methods1756.3.2 Register Summary1766.4 Chipset Register Space1906.4.1 Bridge, GPIO, and LPC Registers - Function 01906.4.1.1 GPIO Support Registers2246.4.1.2 LPC Support Registers2286.4.2 SMI Status and ACPI Registers - Function 12366.4.2.1 SMI Status Support Registers2376.4.2.2 ACPI Support Registers2476.4.3 IDE Controller Registers - Function 22566.4.3.1 IDE Controller Support Registers2606.4.4 Audio Registers - Function 32626.4.4.1 Audio Support Registers2636.4.5 X-Bus Expansion Interface - Function 52776.4.5.1 X-Bus Expansion Support Registers2816.4.6 USB Controller Registers - PCIUSB2836.4.7 ISA Legacy Register Space296Video Processor Module3117.1 Module Architecture3127.2 Functional Description3137.2.1 Video Input Port (VIP)3157.2.1.1 Direct Video Mode3167.2.1.2 Direct VBI Mode3167.2.1.3 Capture Video Mode3167.2.1.4 Capture VBI Mode3197.2.2 Video Block3207.2.2.1 Video Input Formatter3207.2.2.2 Horizontal Downscaler with 4-Tap Filtering3217.2.2.3 Line Buffers3227.2.2.4 Formatter3227.2.2.5 2-Tap Vertical and Horizontal Upscalers3227.2.3 Mixer/Blender Block3237.2.3.1 YUV to RGB CSC in Video Data Path3257.2.3.2 Gamma Correction3257.2.3.3 RGB to YUV CSC3257.2.3.4 1/2 Y Flicker Filter3257.2.3.5 Color/Chroma Key3257.2.3.6 Color/Chroma Key and Mixer/Blender3257.2.4 TVOUT Block3297.2.4.1 Flicker Filter and Scan Rate Conversion3297.2.4.2 Pre-Encoder Horizontal Scaler3307.2.4.3 Video Output Port (VOP)3307.2.4.4 TV Encoder Timing Generator3307.2.4.5 TV Encoder3307.2.5 VESA DDSC2B and DPMS Support3307.2.6 Integrated DACs3307.2.7 TFT Interface3317.2.8 Integrated PLL3327.3 Register Descriptions3337.3.1 Register Summary3337.3.2 Video Processor Registers - Function 43367.3.2.1 Video Processor Support Registers - F4BAR03387.3.2.2 VIP Support Registers - F4BAR2359Debugging and Monitoring3638.1 Testability (JTAG)3638.1.1 Mandatory Instruction Support3638.1.2 Optional Instruction Support3638.1.3 JTAG Chain363Electrical Specifications3659.1 General Specifications3659.1.1 Electro Static Discharge (ESD)3659.1.2 Power/Ground Connections and Decoupling3659.1.3 Absolute Maximum Ratings3659.1.4 Operating Conditions3669.1.5 DC Current3679.1.5.1 Power State Parameter Definitions3679.1.5.2 Definition and Measurement Techniques of Current Parameters3679.1.5.3 Definition of System Conditions for Measuring On Parameters3689.1.5.4 DC Current Measurements3689.1.6 Ball Capacitance and Inductance3699.1.7 Pull-Up and Pull-Down Resistors3709.2 DC Characteristics3719.2.1 INAB DC Characteristics3729.2.2 INBTN DC Characteristics3729.2.3 INPCI DC Characteristics3729.2.4 INSTRP DC Characteristics3739.2.5 INT DC Characteristics3739.2.6 INTS DC Characteristics3739.2.7 INTS1 DC Characteristics3739.2.8 INUSB DC Characteristics3749.2.9 OAC97 DC Characteristics3749.2.10 ODn DC Characteristics3749.2.11 ODPCI DC Characteristics3759.2.12 Op/n DC Characteristics3759.2.13 OPCI DC Characteristics3759.2.14 OUSB DC Characteristics3759.2.15 TSp/n DC Characteristics3759.2.15.1 Exceptions3759.3 AC Characteristics3769.3.1 Memory Controller Interface3779.3.2 Video Port (VP) Interface3809.3.3 CRT and TFT Interface3829.3.4 TV Interface3849.3.5 ACCESS.bus Interface3859.3.6 PCI Bus3889.3.6.1 Measurement and Test Conditions3929.3.7 Sub-ISA Interface3949.3.8 LPC Interface3989.3.9 IDE Interface Timing3999.3.10 Universal Serial Bus (USB)4179.3.11 Serial Port (UART)4219.3.12 Fast IR Port Timing4229.3.13 Parallel Port Timing4239.3.13.1 Extended Capabilities Port (ECP) Timing4259.3.14 Audio Interface Timing (AC97)4279.3.15 Power Management4329.3.16 Power-Up Sequencing4339.3.17 JTAG Interface435Package Specifications43710.1 Thermal Characteristics43710.1.1 Heatsink Considerations43810.2 Physical Dimensions439Support Documentation441A.1 Order Information441A.2 Macrovision Product Notice441A.3 Data Book Revision History442Dimensioni: 3,42 MBPagine: 443Language: EnglishApri il manuale
