Scheda Tecnica (AT91SAM9X25-EK)SommarioSection 15Introduction51.1 Scope51.2 Applicable Documents6Section 27Kit Contents72.1 Deliverables72.2 Evaluation Board Specifications82.3 Electrostatic Warning9Section 310Power Up103.1 Power Up the Board103.2 DevStart103.3 Recovery Procedure113.4 Sample Code and Technical Support11Section 412Evaluation Kit Hardware124.1 Introduction124.2 Computer Module (CM)144.2.1 CM Board Overview144.2.2 Equipment List144.2.3 Function Blocks164.2.4 Configuration254.2.5 Connectors264.2.6 Schematics274.3 EK Board Description324.3.1 EK Board Overview324.3.2 Equipment List334.3.3 Function Blocks344.3.4 Configuration504.3.5 Connectors564.3.6 Schematics744.4 Optional Display Module (DM) Board Hardware894.4.1 DM Board Overview894.4.2 Equipment List894.4.3 Function Blocks894.4.4 Schematics93Section 594Revision History945.1 Revision History94Dimensioni: 6,38 MBPagine: 95Language: EnglishApri il manuale
Scheda Tecnica (AT91SAM9X25-EK)SommarioDescription11. Features22. Block Diagram43. Signal Description54. Package and Pinout104.1 Overview of the 217-ball BGA Package104.2 I/O Description104.2.1 Reset State114.3 217-ball BGA Package Pinout125. Power Considerations185.1 Power Supplies186. Memories196.1 Memory Mapping206.2 Embedded Memories206.2.1 Internal SRAM206.2.2 Internal ROM206.3 External Memories206.3.1 External Bus Interface206.3.2 Static Memory Controller216.3.3 DDR2SDR Controller217. System Controller227.1 Chip Identification247.2 Backup Section248. Peripherals248.1 Peripheral Mapping248.2 Peripheral Identifiers248.3 Peripheral Signal Multiplexing on I/O Lines269. ARM926EJ-S™279.1 Description279.2 Embedded Characteristics289.3 Block Diagram299.4 ARM9EJ-S Processor309.4.1 ARM9EJ-S Operating States309.4.2 Switching State309.4.3 Instruction Pipelines309.4.4 Memory Access309.4.5 Jazelle Technology309.4.6 ARM9EJ-S Operating Modes319.4.7 ARM9EJ-S Registers319.4.7.1 Status Registers329.4.7.2 Exceptions339.4.8 ARM Instruction Set Overview349.4.9 New ARM Instruction Set359.4.10 Thumb Instruction Set Overview369.5 CP15 Coprocessor379.5.1 CP15 Registers Access389.6 Memory Management Unit (MMU)399.6.1 Access Control Logic399.6.2 Translation Look-aside Buffer (TLB)399.6.3 Translation Table Walk Hardware409.6.4 MMU Faults409.7 Caches and Write Buffer409.7.1 Instruction Cache (ICache)409.7.2 Data Cache (DCache) and Write Buffer419.7.2.1 DCache419.7.2.2 Write Buffer419.8 Bus Interface Unit429.8.1 Supported Transfers429.8.2 Thumb Instruction Fetches429.8.3 Address Alignment4210. Debug and Test4310.1 Description4310.2 Embedded Characteristics4310.3 Block Diagram4410.4 Application Examples4510.4.1 Debug Environment4510.4.2 Test Environment4610.5 Debug and Test Pin Description4710.6 Functional Description4810.6.1 Test Pin4810.6.2 EmbeddedICE™4810.6.3 JTAG Signal Description4810.6.4 Debug Unit4810.6.5 IEEE 1149.1 JTAG Boundary Scan4910.6.6 JTAG ID Code Register5011. Boot Strategies5111.1 ROM Code5111.2 Flow Diagram5111.3 Chip Setup5211.4 NVM Boot5211.4.1 NVM Boot Sequence5211.4.2 NVM Bootloader Program Description5411.4.3 Valid Code Detection5511.4.3.1 ARM Exception Vectors Check5511.4.3.2 boot.bin File Check5611.4.4 Detailed Memory Boot Procedures5611.4.4.1 NAND Flash Boot: NAND Flash Detection5611.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction5911.4.4.3 SD Card Boot6011.4.4.4 SPI Flash Boot6111.4.4.5 TWI EEPROM Boot6111.4.5 Hardware and Software Constraints6111.5 SAM-BA Monitor6311.5.1 Command List6311.5.2 DBGU Serial Port6411.5.2.1 Supported External Crystal/External Clocks6411.5.2.2 Xmodem Protocol6411.5.3 USB Device Port6511.5.3.1 Supported External Crystal / External Clocks6511.5.3.2 USB Class6511.5.3.3 Enumeration Process6511.5.3.4 Communication Endpoints6612. Boot Sequence Controller (BSC)6712.1 Description6712.2 Embedded Characteristics6712.3 Product Dependencies6712.4 Boot Sequence Controller (BSC) User Interface6812.4.1 Boot Sequence Configuration Register6913. Advanced Interrupt Controller (AIC)7013.1 Description7013.2 Embedded Characteristics7013.3 Block Diagram7113.4 Application Block Diagram7113.5 AIC Detailed Block Diagram7113.6 I/O Line Description7213.7 Product Dependencies7213.7.1 I/O Lines7213.7.2 Power Management7213.7.3 Interrupt Sources7213.8 Functional Description7313.8.1 Interrupt Source Control7313.8.1.1 Interrupt Source Mode7313.8.1.2 Interrupt Source Enabling7313.8.1.3 Interrupt Clearing and Setting7313.8.1.4 Interrupt Status7313.8.2 Interrupt Latencies7513.8.3 Normal Interrupt7613.8.3.1 Priority Controller7613.8.3.2 Interrupt Nesting7613.8.3.3 Interrupt Vectoring7713.8.3.4 Interrupt Handlers7713.8.4 Fast Interrupt7813.8.4.1 Fast Interrupt Source7813.8.4.2 Fast Interrupt Control7813.8.4.3 Fast Interrupt Vectoring7813.8.4.4 Fast Interrupt Handlers7913.8.4.5 Fast Forcing7913.8.5 Protect Mode8013.8.6 Spurious Interrupt8113.8.7 General Interrupt Mask8113.9 Write Protection Registers8213.10 Advanced Interrupt Controller (AIC) User Interface8313.10.1 Base Address8313.10.2 AIC Source Mode Register8413.10.3 AIC Source Vector Register8513.10.4 AIC Interrupt Vector Register8613.10.5 AIC FIQ Vector Register8713.10.6 AIC Interrupt Status Register8813.10.7 AIC Interrupt Pending Register8913.10.8 AIC Interrupt Mask Register9013.10.9 AIC Core Interrupt Status Register9113.10.10 AIC Interrupt Enable Command Register9213.10.11 AIC Interrupt Disable Command Register9313.10.12 AIC Interrupt Clear Command Register9413.10.13 AIC Interrupt Set Command Register9513.10.14 AIC End of Interrupt Command Register9613.10.15 AIC Spurious Interrupt Vector Register9713.10.16 AIC Debug Control Register9813.10.17 AIC Fast Forcing Enable Register9913.10.18 AIC Fast Forcing Disable Register10013.10.19 AIC Fast Forcing Status Register10113.10.20 AIC Write Protect Mode Register10213.10.21 AIC Write Protect Status Register10314. Reset Controller (RSTC)10414.1 Description10414.2 Embedded Characteristics10414.3 Block Diagram10514.4 Functional Description10614.4.1 Reset Controller Overview10614.4.2 NRST Manager10614.4.2.1 NRST Signal10614.4.2.2 NRST External Reset Control10714.4.3 BMS Sampling10714.4.4 Reset States10714.4.4.1 General Reset10714.4.4.2 Wake-up Reset10814.4.4.3 User Reset10914.4.4.4 Software Reset11014.4.4.5 Watchdog Reset11114.4.5 Reset State Priorities11214.4.6 Reset Controller Status Register11314.5 Reset Controller (RSTC) User Interface11414.5.1 Reset Controller Control Register11514.5.2 Reset Controller Status Register11614.5.3 Reset Controller Mode Register11715. Real-time Clock (RTC)11815.1 Description11815.2 Embedded Characteristics11815.3 Block Diagram11915.4 Product Dependencies12015.4.1 Power Management12015.4.2 Interrupt12015.5 Functional Description12015.5.1 Reference Clock12015.5.2 Timing12015.5.3 Alarm12015.5.4 Error Checking when Programming12115.5.5 Updating Time/Calendar12115.6 Real-time Clock (RTC) User Interface12315.6.1 RTC Control Register12415.6.2 RTC Mode Register12515.6.3 RTC Time Register12615.6.4 RTC Calendar Register12715.6.5 RTC Time Alarm Register12815.6.6 RTC Calendar Alarm Register12915.6.7 RTC Status Register13015.6.8 RTC Status Clear Command Register13115.6.9 RTC Interrupt Enable Register13215.6.10 RTC Interrupt Disable Register13315.6.11 RTC Interrupt Mask Register13415.6.12 RTC Valid Entry Register13516. Periodic Interval Timer (PIT)13616.1 Description13616.2 Embedded Characteristics13616.3 Block Diagram13716.4 Functional Description13816.5 Periodic Interval Timer (PIT) User Interface13916.5.1 Periodic Interval Timer Mode Register14016.5.2 Periodic Interval Timer Status Register14116.5.3 Periodic Interval Timer Value Register14216.5.4 Periodic Interval Timer Image Register14317. Watchdog Timer (WDT)14417.1 Description14417.2 Embedded Characteristics14417.3 Block Diagram14517.4 Functional Description14617.5 Watchdog Timer (WDT) User Interface14817.5.1 Watchdog Timer Control Register14917.5.2 Watchdog Timer Mode Register15017.5.3 Watchdog Timer Status Register15118. Shutdown Controller (SHDWC)15218.1 Description15218.2 Embedded Characteristics15218.3 Block Diagram15318.4 I/O Lines Description15418.5 Product Dependencies15418.5.1 Power Management15418.6 Functional Description15518.7 Shutdown Controller (SHDWC) User Interface15618.7.1 Shutdown Control Register15718.7.2 Shutdown Mode Register15818.7.3 Shutdown Status Register15919. General Purpose Backup Registers (GPBR)16019.1 Description16019.2 Embedded Characteristics16019.3 General Purpose Backup Registers (GPBR) User Interface16119.3.1 General Purpose Backup Register x16220. Slow Clock Controller (SCKC)16320.1 Description16320.2 Embedded Characteristics16320.3 Block Diagram16320.3.1 Switch from Internal 32 kHz RC Oscillator to 32768 Hz Crystal Oscillator16420.3.2 Bypass the 32768 Hz Oscillator16420.3.3 Switch from 32768 Hz Crystal Oscillator to Internal 32 kHz RC Oscillator16420.4 Slow Clock Configuration (SCKC) User Interface16520.4.1 Slow Clock Configuration Register16621. Clock Generator (CKGR)16721.1 Description16721.2 Embedded Characteristics16721.3 CKGR Block Diagram16821.4 Slow Clock Selection16921.4.1 Switch from Internal 32 kHz RC Oscillator to the 32768 Hz Crystal16921.4.2 Bypass the 32768 Hz Oscillator16921.4.3 Switch from the 32768 Hz Crystal to Internal 32 kHz RC Oscillator17021.4.4 Slow Clock Configuration Register17121.5 Main Clock17221.6 Main Clock Selection17321.6.1 Fast wake-up17321.6.2 Switch from Internal 12 MHz RC Oscillator to the 12 MHz Crystal17421.6.3 Bypass the 12 MHz Oscillator17421.6.4 Switch from the 12 MHz Crystal to Internal 12 MHz RC Oscillator17421.6.5 12 MHz Fast RC Oscillator17421.6.6 12 to 16 MHz Crystal Oscillator17421.6.7 Main Clock Oscillator Selection17521.6.8 Main Clock Frequency Counter17521.7 Divider and PLLA Block17521.7.1 Divider and Phase Lock Loop Programming17621.8 UTMI Phase Lock Loop Programming17622. Power Management Controller (PMC)17722.1 Description17722.2 Embedded Characteristics17722.3 Master Clock Controller17822.4 Block Diagram17922.5 Processor Clock Controller17922.6 USB Device and Host Clocks18022.7 LP-DDR/DDR2 Clock18022.8 Software Modem Clock18022.9 Peripheral Clock Controller18022.10 Programmable Clock Output Controller18122.11 Programming Sequence18122.12 Clock Switching Details18422.12.1 Master Clock Switching Timings18422.12.2 Clock Switching Waveforms18522.13 Power Management Controller (PMC) User Interface18722.13.1 PMC System Clock Enable Register18822.13.2 PMC System Clock Disable Register18922.13.3 PMC System Clock Status Register19022.13.4 PMC Peripheral Clock Enable Register19122.13.5 PMC Peripheral Clock Disable Register19222.13.6 PMC Peripheral Clock Status Register19322.13.7 PMC UTMI Clock Configuration Register19422.13.8 PMC Clock Generator Main Oscillator Register19522.13.9 PMC Clock Generator Main Clock Frequency Register19622.13.10 PMC Clock Generator PLLA Register19722.13.11 PMC Master Clock Register19822.13.12 PMC USB Clock Register20022.13.13 PMC SMD Clock Register20122.13.14 PMC Programmable Clock Register20222.13.15 PMC Interrupt Enable Register20322.13.16 PMC Interrupt Disable Register20422.13.17 PMC Status Register20522.13.18 PMC Interrupt Mask Register20722.13.19 PLL Charge Pump Current Register20822.13.20 PMC Write Protect Mode Register20922.13.21 PMC Write Protect Status Register21022.13.22 PMC Peripheral Control Register21123. Parallel Input/Output (PIO) Controller21223.1 Description21223.2 Embedded Characteristics21223.3 Block Diagram21323.4 Product Dependencies21423.4.1 Pin Multiplexing21423.4.2 External Interrupt Lines21423.4.3 Power Management21423.4.4 Interrupt Generation21423.5 Functional Description21523.5.1 Pull-up and Pull-down Resistor Control21623.5.2 I/O Line or Peripheral Function Selection21623.5.3 Peripheral A or B or C or D Selection21623.5.4 Output Control21723.5.5 Synchronous Data Output21723.5.6 Multi Drive Control (Open Drain)21723.5.7 Output Line Timings21723.5.8 Inputs21823.5.9 Input Glitch and Debouncing Filters21823.5.10 Input Edge/Level Interrupt21923.5.10.1 Example22023.5.10.2 Interrupt Mode Configuration22123.5.10.3 Edge or Level Detection Configuration22123.5.10.4 Falling/Rising Edge or Low/High Level Detection Configuration.22123.5.11 I/O Lines Lock22123.5.12 Programmable I/O Delays22123.5.13 Programmable I/O Drive22223.5.14 Programmable Schmitt Trigger22223.5.15 Write Protection Registers22323.6 I/O Lines Programming Example22423.7 Parallel Input/Output Controller (PIO) User Interface22523.7.1 PIO Enable Register22823.7.2 PIO Disable Register22923.7.3 PIO Status Register23023.7.4 PIO Output Enable Register23123.7.5 PIO Output Disable Register23223.7.6 PIO Output Status Register23323.7.7 PIO Input Filter Enable Register23423.7.8 PIO Input Filter Disable Register23523.7.9 PIO Input Filter Status Register23623.7.10 PIO Set Output Data Register23723.7.11 PIO Clear Output Data Register23823.7.12 PIO Output Data Status Register23923.7.13 PIO Pin Data Status Register24023.7.14 PIO Interrupt Enable Register24123.7.15 PIO Interrupt Disable Register24223.7.16 PIO Interrupt Mask Register24323.7.17 PIO Interrupt Status Register24423.7.18 PIO Multi-driver Enable Register24523.7.19 PIO Multi-driver Disable Register24623.7.20 PIO Multi-driver Status Register24723.7.21 PIO Pull Up Disable Register24823.7.22 PIO Pull Up Enable Register24923.7.23 PIO Pull Up Status Register25023.7.24 PIO Peripheral ABCD Select Register 125123.7.25 PIO Peripheral ABCD Select Register 225223.7.26 PIO Input Filter Slow Clock Disable Register25323.7.27 PIO Input Filter Slow Clock Enable Register25423.7.28 PIO Input Filter Slow Clock Status Register25523.7.29 PIO Slow Clock Divider Debouncing Register25623.7.30 PIO Pad Pull Down Disable Register25723.7.31 PIO Pad Pull Down Enable Register25823.7.32 PIO Pad Pull Down Status Register25923.7.33 PIO Output Write Enable Register26023.7.34 PIO Output Write Disable Register26123.7.35 PIO Output Write Status Register26223.7.36 PIO Additional Interrupt Modes Enable Register26323.7.37 PIO Additional Interrupt Modes Disable Register26423.7.38 PIO Additional Interrupt Modes Mask Register26523.7.39 PIO Edge Select Register26623.7.40 PIO Level Select Register26723.7.41 PIO Edge/Level Status Register26823.7.42 PIO Falling Edge/Low Level Select Register26923.7.43 PIO Rising Edge/High Level Select Register27023.7.44 PIO Fall/Rise - Low/High Status Register27123.7.45 PIO Lock Status Register27223.7.46 PIO Write Protect Mode Register27323.7.47 PIO Write Protect Status Register27423.7.48 PIO Schmitt Trigger Register27523.7.49 PIO I/O Delay Register27623.7.50 PIO I/O Drive Register 127723.7.51 PIO I/O Drive Register 227824. Debug Unit (DBGU)27924.1 Description27924.2 Embedded Characteristics27924.3 Block Diagram28024.4 Product Dependencies28124.4.1 I/O Lines28124.4.2 Power Management28124.4.3 Interrupt Source28124.5 UART Operations28124.5.1 Baud Rate Generator28124.5.2 Receiver28224.5.2.1 Receiver Reset, Enable and Disable28224.5.2.2 Start Detection and Data Sampling28224.5.2.3 Receiver Ready28324.5.2.4 Receiver Overrun28324.5.2.5 Parity Error28324.5.2.6 Receiver Framing Error28424.5.3 Transmitter28424.5.3.1 Transmitter Reset, Enable and Disable28424.5.3.2 Transmit Format28424.5.3.3 Transmitter Control28424.5.4 DMA Support28524.5.5 Test Modes28524.5.6 Debug Communication Channel Support28624.5.7 Chip Identifier28724.5.8 ICE Access Prevention28724.6 Debug Unit (DBGU) User Interface28824.6.1 Debug Unit Control Register28924.6.2 Debug Unit Mode Register29024.6.3 Debug Unit Interrupt Enable Register29124.6.4 Debug Unit Interrupt Disable Register29224.6.5 Debug Unit Interrupt Mask Register29324.6.6 Debug Unit Status Register29424.6.7 Debug Unit Receiver Holding Register29524.6.8 Debug Unit Transmit Holding Register29524.6.9 Debug Unit Baud Rate Generator Register29624.6.10 Debug Unit Chip ID Register29724.6.11 Debug Unit Chip ID Extension Register30124.6.12 Debug Unit Force NTRST Register30225. Bus Matrix (MATRIX)30325.1 Description30325.2 Embedded Characteristics30325.2.1 Matrix Masters30425.2.2 Matrix Slaves30425.2.3 Master to Slave Access30525.3 Memory Mapping30525.4 Special Bus Granting Mechanism30525.4.1 No Default Master30625.4.2 Last Access Master30625.4.3 Fixed Default Master30625.5 Arbitration30625.5.1 Arbitration Scheduling30725.5.1.1 Undefined Length Burst Arbitration30725.5.1.2 Slot Cycle Limit Arbitration30725.5.2 Arbitration Priority Scheme30825.5.2.1 Fixed Priority Arbitration30825.5.2.2 Round-Robin Arbitration30825.6 Register Write Protection30925.7 Bus Matrix (MATRIX) User Interface31025.7.1 Bus Matrix Master Configuration Registers31225.7.2 Bus Matrix Slave Configuration Registers31425.7.3 Bus Matrix Priority Registers A For Slaves31625.7.4 Bus Matrix Priority Registers B For Slaves31725.7.5 Bus Matrix Master Remap Control Register31825.7.6 EBI Chip Select Assignment Register31925.7.7 Write Protection Mode Register32125.7.8 Write Protection Status Register32226. External Bus Interface (EBI)32326.1 Description32326.2 Embedded Characteristics32326.3 EBI Block Diagram32426.4 I/O Lines Description32526.5 Application Example32626.5.1 Hardware Interface32626.5.2 Product Dependencies32826.5.2.1 I/O Lines32826.5.3 Functional Description32826.5.3.1 Bus Multiplexing32826.5.3.2 Pull-up and Pull-down Control32826.5.3.3 Drive Level and Delay Control32926.5.3.4 Power supplies33026.5.3.5 Static Memory Controller33126.5.3.6 DDR2SDRAM Controller33126.5.3.7 Programmable Multibit ECC Controller33226.5.3.8 NAND Flash Support33226.5.4 Implementation Examples33326.5.4.1 2x8-bit DDR2 on EBI33326.5.4.2 16-bit LPDDR on EBI33426.5.4.3 16-bit SDRAM on EBI33526.5.4.4 2x16-bit SDRAM on EBI33626.5.4.5 8-bit NAND Flash with NFD0_ON_D16 = 033726.5.4.6 16-bit NAND Flash with NFD0_ON_D16 = 033826.5.4.7 8-bit NAND Flash with NFD0_ON_D16 = 133926.5.4.8 16-bit NAND Flash with NFD0_ON_D16 = 134026.5.4.9 NOR Flash on NCS034127. Programmable Multibit ECC Controller (PMECC)34227.1 Description34227.2 Embedded Characteristics34227.3 Block Diagram34327.4 Functional Description34427.4.1 MLC/SLC Write Page Operation using PMECC34627.4.1.1 SLC/MLC Write Operation with Spare Enable Bit Set34727.4.1.2 MLC/SLC Write Operation with Spare Area Disabled34727.4.2 MLC/SLC Read Page Operation using PMECC34827.4.2.1 MLC/SLC Read Operation with Spare Decoding34827.4.2.2 MLC/SLC Read Operation34827.4.2.3 MLC/SLC User Read ECC Area34927.5 Software Implementation34927.5.1 Remainder Substitution Procedure34927.5.2 Find the Error Location Polynomial Sigma(x)35027.5.3 Find the Error Position35327.6 Programmable Multibit ECC Controller (PMECC) User Interface35427.6.1 PMECC Configuration Register35627.6.2 PMECC Spare Area Size Register35827.6.3 PMECC Start Address Register35927.6.4 PMECC End Address Register36027.6.5 PMECC Clock Control Register36127.6.6 PMECC Control Register36227.6.7 PMECC Status Register36327.6.8 PMECC Interrupt Enable Register36427.6.9 PMECC Interrupt Disable Register36527.6.10 PMECC Interrupt Mask Register36627.6.11 PMECC Interrupt Status Register36727.6.12 PMECC ECC x Register36827.6.13 PMECC Remainder x Register36928. Programmable Multibit ECC Error Location Controller (PMERRLOC)37028.1 Description37028.2 Embedded Characteristics37028.3 Block Diagram37028.4 Functional Description37128.5 Programmable Multibit ECC Error Location Controller (PMERRLOC) User Interface37228.5.1 Error Location Configuration Register37328.5.2 Error Location Primitive Register37428.5.3 Error Location Enable Register37528.5.4 Error Location Disable Register37628.5.5 Error Location Status Register37728.5.6 Error Location Interrupt Enable Register37828.5.7 Error Location Interrupt Disable Register37928.5.8 Error Location Interrupt Mask Register38028.5.9 Error Location Interrupt Status Register38128.5.10 Error Location SIGMAx Register38228.5.11 PMECC Error Locationx Register38329. Static Memory Controller (SMC)38429.1 Description38429.2 Embedded Characteristics38429.3 I/O Lines Description38529.4 Multiplexed Signals38529.5 Application Example38629.5.1 Hardware Interface38629.6 Product Dependencies38629.6.1 I/O Lines38629.7 External Memory Mapping38729.8 Connection to External Devices38729.8.1 Data Bus Width38729.8.2 Byte Write or Byte Select Access38729.8.2.1 Byte Write Access38929.8.2.2 Byte Select Access38929.8.2.3 Signal Multiplexing39029.9 Standard Read and Write Protocols39129.9.1 Read Waveforms39129.9.1.1 NRD Waveform39129.9.1.2 NCS Waveform39129.9.1.3 Read Cycle39229.9.1.4 Null Delay Setup and Hold39229.9.1.5 Null Pulse39229.9.2 Read Mode39329.9.2.1 Read is Controlled by NRD (READ_MODE = 1):39329.9.2.2 Read is Controlled by NCS (READ_MODE = 0)39329.9.3 Write Waveforms39429.9.3.1 NWE Waveforms39429.9.3.2 NCS Waveforms39429.9.3.3 Write Cycle39529.9.3.4 Null Delay Setup and Hold39529.9.3.5 Null Pulse39629.9.4 Write Mode39629.9.4.1 Write is Controlled by NWE (WRITE_MODE = 1)39629.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0)39729.9.5 Write Protected Registers39829.9.6 Coding Timing Parameters39829.9.7 Reset Values of Timing Parameters39829.9.8 Usage Restriction39829.10 Automatic Wait States39929.10.1 Chip Select Wait States39929.10.2 Early Read Wait State40029.10.3 Reload User Configuration Wait State40229.10.3.1 User Procedure40229.10.3.2 Slow Clock Mode Transition40229.10.4 Read to Write Wait State40229.11 Data Float Wait States40229.11.1 READ_MODE40329.11.2 TDF Optimization Enabled (TDF_MODE = 1)40429.11.3 TDF Optimization Disabled (TDF_MODE = 0)40529.12 External Wait40729.12.1 Restriction40729.12.2 Frozen Mode40829.12.3 Ready Mode41029.12.4 NWAIT Latency and Read/Write Timings41229.13 Slow Clock Mode41329.13.1 Slow Clock Mode Waveforms41329.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode41429.14 Asynchronous Page Mode41629.14.1 Protocol and Timings in Page Mode41629.14.2 Byte Access Type in Page Mode41729.14.3 Page Mode Restriction41729.14.4 Sequential and Non-sequential Accesses41729.15 Programmable IO Delays41829.16 Static Memory Controller (SMC) User Interface42029.16.1 SMC Setup Register42129.16.2 SMC Pulse Register42229.16.3 SMC Cycle Register42329.16.4 SMC MODE Register42429.16.5 SMC DELAY I/O Register42629.16.6 SMC Write Protect Mode Register42729.16.7 SMC Write Protect Status Register42830. DDR SDR SDRAM Controller (DDRSDRC)42930.1 Description42930.2 Embedded Characteristics43030.3 DDRSDRC Module Diagram43130.4 Initialization Sequence43230.4.1 SDR-SDRAM Initialization43230.4.2 Low-power DDR1-SDRAM Initialization43230.4.3 DDR2-SDRAM Initialization43330.5 Functional Description43530.5.1 SDRAM Controller Write Cycle43530.5.2 SDRAM Controller Read Cycle44030.5.3 Refresh (Auto-refresh Command)44430.5.4 Power Management44430.5.4.1 Self Refresh Mode44430.5.4.2 Power-down Mode44730.5.4.3 Deep Power-down Mode44830.5.4.4 Reset Mode44930.5.5 Multi-port Functionality44930.5.6 Write Protected Registers45130.6 Software Interface/SDRAM Organization, Address Mapping45230.6.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Four Banks45230.6.2 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Eight Banks45430.6.3 SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width45430.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface45630.7.1 DDRSDRC Mode Register45730.7.2 DDRSDRC Refresh Timer Register45830.7.3 DDRSDRC Configuration Register45930.7.4 DDRSDRC Timing Parameter 0 Register46230.7.5 DDRSDRC Timing Parameter 1 Register46430.7.6 DDRSDRC Timing Parameter 2 Register46530.7.7 DDRSDRC Low-power Register46630.7.8 DDRSDRC Memory Device Register46830.7.9 DDRSDRC DLL Register46930.7.10 DDRSDRC High Speed Register47030.7.11 DDRSDRC Write Protect Mode Register47130.7.12 DDRSDRC Write Protect Status Register47231. DMA Controller (DMAC)47331.1 Description47331.2 Embedded Characteristics47331.2.1 DMA Controller 047431.2.2 DMA Controller 147531.3 Block Diagram47631.4 Functional Description47731.4.1 Basic Definitions47731.4.2 Memory Peripherals47931.4.3 Handshaking Interface48031.4.3.1 Software Handshaking48031.4.4 DMAC Transfer Types48031.4.4.1 Multi-buffer Transfers48131.4.4.2 Programming DMAC for Multiple Buffer Transfers48231.4.4.3 Ending Multi-buffer Transfers48331.4.5 Programming a Channel48331.4.5.1 Programming Examples48331.4.6 Disabling a Channel Prior to Transfer Completion50131.4.6.1 Abnormal Transfer Termination50131.5 DMAC Software Requirements50231.6 Write Protection Registers50331.7 DMA Controller (DMAC) User Interface50431.7.1 DMAC Global Configuration Register50531.7.2 DMAC Enable Register50631.7.3 DMAC Software Single Request Register50731.7.4 DMAC Software Chunk Transfer Request Register50831.7.5 DMAC Software Last Transfer Flag Register50931.7.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register51031.7.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register51131.7.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register51231.7.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register51331.7.10 DMAC Channel Handler Enable Register51431.7.11 DMAC Channel Handler Disable Register51531.7.12 DMAC Channel Handler Status Register51631.7.13 DMAC Channel x [x = 0..7] Source Address Register51731.7.14 DMAC Channel x [x = 0..7] Destination Address Register51831.7.15 DMAC Channel x [x = 0..7] Descriptor Address Register51931.7.16 DMAC Channel x [x = 0..7] Control A Register52031.7.17 DMAC Channel x [x = 0..7] Control B Register52231.7.18 DMAC Channel x [x = 0..7] Configuration Register52431.7.19 DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register52631.7.20 DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register52731.7.21 DMAC Write Protect Mode Register52831.7.22 DMAC Write Protect Status Register52932. USB High Speed Device Port (UDPHS)53032.1 Description53032.2 Embedded Characteristics53032.3 Block Diagram53132.4 Typical Connection53232.5 Product Dependencies53232.5.1 Power Management53232.5.2 Interrupt53232.6 Functional Description53332.6.1 UTMI Transceivers Sharing53332.6.2 USB V2.0 High Speed Device Port Introduction53332.6.3 USB V2.0 High Speed Transfer Types53332.6.4 USB Transfer Event Definitions53432.6.5 USB V2.0 High Speed BUS Transactions53432.6.6 Endpoint Configuration53532.6.7 DPRAM Management53732.6.8 Transfer With DMA53932.6.9 Transfer Without DMA53932.6.10 Handling Transactions with USB V2.0 Device Peripheral54032.6.10.1 Setup Transaction54032.6.10.2 NYET54032.6.10.3 Data IN54132.6.10.4 Bulk IN or Interrupt IN54132.6.10.5 Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host)54132.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host)54232.6.10.7 Isochronous IN54532.6.10.8 High Bandwidth Isochronous Endpoint Handling: IN Example54532.6.10.9 Data OUT54632.6.10.10 Bulk OUT or Interrupt OUT54632.6.10.11 Bulk OUT or Interrupt OUT: Receiving a Packet Under Application Control (Host to Device)54632.6.10.12 Bulk OUT or Interrupt OUT: Sending a Buffer Using DMA (Host To Device)54732.6.10.13 High Bandwidth Isochronous Endpoint OUT54832.6.10.14 Isochronous Endpoint Handling: OUT Example54932.6.10.15 STALL54932.6.11 Speed Identification55032.6.12 USB V2.0 High Speed Global Interrupt55032.6.13 Endpoint Interrupts55032.6.14 Power Modes55232.6.14.1 Controlling Device States55232.6.14.2 Not Powered State55332.6.14.3 Entering Attached State55332.6.14.4 From Powered State to Default State (Reset)55332.6.14.5 From Default State to Address State (Address Assigned)55332.6.14.6 From Address State to Configured State (Device Configured)55332.6.14.7 Entering Suspend State (Bus Activity)55332.6.14.8 Receiving a Host Resume55432.6.14.9 Sending an External Resume55432.6.15 Test Mode55432.7 USB High Speed Device Port (UDPHS) User Interface55532.7.1 UDPHS Control Register55632.7.2 UDPHS Frame Number Register55832.7.3 UDPHS Interrupt Enable Register55932.7.4 UDPHS Interrupt Status Register56032.7.5 UDPHS Clear Interrupt Register56232.7.6 UDPHS Endpoints Reset Register56332.7.7 UDPHS Test Register56432.7.8 UDPHS Endpoint Configuration Register56632.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)56832.7.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints)57032.7.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints)57232.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint)57432.7.13 UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints)57632.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint)57932.7.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints)58232.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint)58332.7.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints)58432.7.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint)58532.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints)58632.7.20 UDPHS Endpoint Status Register (Isochronous Endpoint)58932.7.21 UDPHS DMA Channel Transfer Descriptor59332.7.22 UDPHS DMA Next Descriptor Address Register59432.7.23 UDPHS DMA Channel Address Register59532.7.24 UDPHS DMA Channel Control Register59632.7.25 UDPHS DMA Channel Status Register59833. USB Host High Speed Port (UHPHS)60033.1 Description60033.2 Embedded Characteristics60033.3 Block Diagram60133.4 Typical Connection60233.5 Product Dependencies60333.5.1 I/O Lines60333.5.2 Power Management60333.5.3 Interrupt60433.6 Functional Description60533.6.1 UTMI transceivers Sharing60533.6.2 EHCI60533.6.3 OHCI60534. High Speed MultiMedia Card Interface (HSMCI)60634.1 Description60634.2 Embedded Characteristics60634.3 Block Diagram60734.4 Application Block Diagram60734.5 Pin Name List60834.6 Product Dependencies60834.6.1 I/O Lines60834.6.2 Power Management60834.6.3 Interrupt60934.7 Bus Topology60934.8 High Speed MultiMedia Card Operations61134.8.1 Command - Response Operation61134.8.2 Data Transfer Operation61434.8.3 Read Operation61434.8.4 Write Operation61634.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller61834.8.6 READ_SINGLE_BLOCK Operation using DMA Controller61934.8.6.1 Block Length is Multiple of 461934.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0)62034.8.6.3 Block Length is Not Multiple of 4, with Padding Value (ROPT field in HSMCI_DMA register set to 1)62234.8.7 WRITE_MULTIPLE_BLOCK62334.8.7.1 One Block per Descriptor62334.8.8 READ_MULTIPLE_BLOCK62434.8.8.1 Block Length is a Multiple of 462434.8.8.2 Block Length is Not Multiple of 4. (ROPT field in HSMCI_DMA register set to 0)62534.8.8.3 Block Length is Not a Multiple of 4. (ROPT field in HSMCI_DMA register set to 1)62734.9 SD/SDIO Card Operation62834.9.1 SDIO Data Transfer Type62834.9.2 SDIO Interrupts62934.10 CE-ATA Operation62934.10.1 Executing an ATA Polling Command62934.10.2 Executing an ATA Interrupt Command62934.10.3 Aborting an ATA Command62934.10.4 CE-ATA Error Recovery62934.11 HSMCI Boot Operation Mode63034.11.1 Boot Procedure, Processor Mode63034.11.2 Boot Procedure DMA Mode63034.12 HSMCI Transfer Done Timings63134.12.1 Definition63134.12.2 Read Access63134.12.3 Write Access63134.13 Write Protection Registers63234.14 High Speed MultiMedia Card Interface (HSMCI) User Interface63334.14.1 HSMCI Control Register63434.14.2 HSMCI Mode Register63534.14.3 HSMCI Data Timeout Register63634.14.4 HSMCI SDCard/SDIO Register63734.14.5 HSMCI Argument Register63834.14.6 HSMCI Command Register63934.14.7 HSMCI Block Register64134.14.8 HSMCI Completion Signal Timeout Register64234.14.9 HSMCI Response Register64334.14.10 HSMCI Receive Data Register64434.14.11 HSMCI Transmit Data Register64534.14.12 HSMCI Status Register64634.14.13 HSMCI Interrupt Enable Register64934.14.14 HSMCI Interrupt Disable Register65134.14.15 HSMCI Interrupt Mask Register65334.14.16 HSMCI DMA Configuration Register65534.14.17 HSMCI Configuration Register65634.14.18 H SMCI Write Protect Mode Register65734.14.19 HSMCI Write Protect Status Register65834.14.20 HSMCI FIFOx Memory Aperture65935. Serial Peripheral Interface (SPI)66035.1 Description66035.2 Embedded Characteristics66035.3 Block Diagram66135.4 Application Block Diagram66235.5 Signal Description66235.6 Product Dependencies66235.6.1 I/O Lines66235.6.2 Power Management66335.6.3 Interrupt66335.6.4 Direct Memory Access Controller (DMAC)66335.7 Functional Description66335.7.1 Modes of Operation66335.7.2 Data Transfer66435.7.3 Master Mode Operations66535.7.3.1 Master Mode Block Diagram66635.7.3.2 Master Mode Flow Diagram66735.7.3.3 Clock Generation66835.7.3.4 Transfer Delays66835.7.3.5 Peripheral Selection66935.7.3.6 SPI Direct Access Memory Controller (DMAC)66935.7.3.7 Peripheral Chip Select Decoding67035.7.3.8 Peripheral Deselection without DMA67035.7.3.9 Peripheral Deselection with DMAC67135.7.3.10 Mode Fault Detection67235.7.4 SPI Slave Mode67235.7.5 Write Protected Registers67335.8 Serial Peripheral Interface (SPI) User Interface67435.8.1 SPI Control Register67535.8.2 SPI Mode Register67635.8.3 SPI Receive Data Register67835.8.4 SPI Transmit Data Register67935.8.5 SPI Status Register68035.8.6 SPI Interrupt Enable Register68135.8.7 SPI Interrupt Disable Register68235.8.8 SPI Interrupt Mask Register68335.8.9 SPI Chip Select Register68435.8.10 SPI Write Protection Mode Register68635.8.11 SPI Write Protection Status Register68736. Timer Counter (TC)68836.1 Description68836.2 Embedded Characteristics68836.3 Block Diagram68936.4 Pin Name List69036.5 Product Dependencies69036.5.1 I/O Lines69036.5.2 Power Management69036.5.3 Interrupt69036.6 Functional Description69136.6.1 TC Description69136.6.2 32-bit Counter69136.6.3 Clock Selection69136.6.4 Clock Control69336.6.5 TC Operating Modes69336.6.6 Trigger69436.6.7 Capture Operating Mode69436.6.8 Capture Registers A and B69436.6.9 Trigger Conditions69436.6.10 Waveform Operating Mode69636.6.11 Waveform Selection69636.6.11.1 WAVSEL = 0069836.6.11.2 WAVSEL = 1069936.6.11.3 WAVSEL = 0170036.6.11.4 WAVSEL = 1170136.6.12 External Event/Trigger Conditions70236.6.13 Output Controller70236.7 Timer Counter (TC) User Interface70336.7.1 TC Channel Control Register70436.7.2 TC Channel Mode Register: Capture Mode70536.7.3 TC Channel Mode Register: Waveform Mode70736.7.4 TC Counter Value Register71136.7.5 TC Register A71236.7.6 TC Register B71236.7.7 TC Register C71336.7.8 TC Status Register71436.7.9 TC Interrupt Enable Register71636.7.10 TC Interrupt Disable Register71736.7.11 TC Interrupt Mask Register71836.7.12 TC Block Control Register71936.7.13 TC Block Mode Register72037. Pulse Width Modulation Controller (PWM)72137.1 Description72137.2 Embedded characteristics72137.3 Block Diagram72237.4 I/O Lines Description72237.5 Product Dependencies72337.5.1 I/O Lines72337.5.2 Power Management72337.5.3 Interrupt Sources72337.6 Functional Description72437.6.1 PWM Clock Generator72437.6.2 PWM Channel72537.6.2.1 Block Diagram72537.6.2.2 Waveform Properties72537.6.3 PWM Controller Operations72837.6.3.1 Initialization72837.6.3.2 Source Clock Selection Criteria72837.6.3.3 Changing the Duty Cycle or the Period72837.6.3.4 Interrupts72937.7 Pulse Width Modulation Controller (PWM) User Interface73037.7.1 PWM Mode Register73137.7.2 PWM Enable Register73237.7.3 PWM Disable Register73237.7.4 PWM Status Register73337.7.5 PWM Interrupt Enable Register73437.7.6 PWM Interrupt Disable Register73537.7.7 PWM Interrupt Mask Register73637.7.8 PWM Interrupt Status Register73737.7.9 PWM Channel Mode Register73837.7.10 PWM Channel Duty Cycle Register73937.7.11 PWM Channel Period Register74037.7.12 PWM Channel Counter Register74137.7.13 PWM Channel Update Register74238. Two-wire Interface (TWI)74338.1 Description74338.2 Embedded Characteristics74438.3 List of Abbreviations74438.4 Block Diagram74538.5 Application Block Diagram74538.5.1 I/O Lines Description74538.6 Product Dependencies74638.6.1 I/O Lines74638.6.2 Power Management74638.6.3 Interrupt74638.7 Functional Description74738.7.1 Transfer Format74738.7.2 Modes of Operation74738.8 Master Mode74838.8.1 Definition74838.8.2 Application Block Diagram74838.8.3 Programming Master Mode74838.8.4 Master Transmitter Mode74838.8.5 Master Receiver Mode75038.8.6 Internal Address75238.8.6.1 7-bit Slave Addressing75238.8.6.2 10-bit Slave Addressing75338.8.7 Using the DMA Controller75338.8.7.1 Data Transmit with the DMA75338.8.7.2 Data Receive with the DMA75338.8.8 SMBUS Quick Command (Master Mode Only)75438.8.9 Read-write Flowcharts75438.9 Multi-master Mode76138.9.1 Definition76138.9.2 Different Multi-master Modes76138.9.2.1 TWI as Master Only76138.9.2.2 TWI as Master or Slave76138.10 Slave Mode76438.10.1 Definition76438.10.2 Application Block Diagram76438.10.3 Programming Slave Mode76438.10.4 Receiving Data76438.10.4.1 Read Sequence76438.10.4.2 Write Sequence76538.10.4.3 Clock Synchronization Sequence76538.10.4.4 General Call76538.10.5 Data Transfer76538.10.5.1 Read Operation76538.10.5.2 Write Operation76638.10.5.3 General Call76638.10.5.4 Clock Synchronization76738.10.5.5 Reversal after a Repeated Start76938.10.6 Read Write Flowcharts77038.11 Write Protection System77138.12 Two-wire Interface (TWI) User Interface77238.12.1 TWI Control Register77338.12.2 TWI Master Mode Register77538.12.3 TWI Slave Mode Register77638.12.4 TWI Internal Address Register77738.12.5 TWI Clock Waveform Generator Register77838.12.6 TWI Status Register77938.12.7 TWI Interrupt Enable Register78238.12.8 TWI Interrupt Disable Register78338.12.9 TWI Interrupt Mask Register78438.12.10 TWI Receive Holding Register78538.12.11 TWI Transmit Holding Register78638.12.12 TWI Write Protection Mode Register78738.12.13 TWI Write Protection Status Register78839. Universal Synchronous Asynchronous Receiver Transmitter (USART)78939.1 Description78939.2 Embedded Characteristics79039.3 Block Diagram79139.4 Application Block Diagram79239.5 I/O Lines Description79339.6 Product Dependencies79339.6.1 I/O Lines79339.6.2 Power Management79439.6.3 Interrupt79439.7 Functional Description79539.7.1 Baud Rate Generator79639.7.1.1 Baud Rate in Asynchronous Mode79639.7.1.2 Fractional Baud Rate in Asynchronous Mode79839.7.1.3 Baud Rate in Synchronous Mode or SPI Mode79839.7.1.4 Baud Rate in ISO 7816 Mode79939.7.2 Receiver and Transmitter Control80039.7.3 Synchronous and Asynchronous Modes80039.7.3.1 Transmitter Operations80039.7.3.2 Manchester Encoder80139.7.3.3 Asynchronous Receiver80339.7.3.4 Manchester Decoder80439.7.3.5 Radio Interface: Manchester Encoded USART Application80639.7.3.6 Synchronous Receiver80739.7.3.7 Receiver Operations80739.7.3.8 Parity80839.7.3.9 Multidrop Mode80939.7.3.10 Transmitter Timeguard80939.7.3.11 Receiver Time-out81039.7.3.12 Framing Error81139.7.3.13 Transmit Break81239.7.3.14 Receive Break81339.7.3.15 Hardware Handshaking81339.7.4 ISO7816 Mode81439.7.4.1 ISO7816 Mode Overview81439.7.4.2 Protocol T = 081439.7.4.3 Protocol T = 181639.7.5 IrDA Mode81639.7.5.1 IrDA Modulation81639.7.5.2 IrDA Baud Rate81739.7.5.3 IrDA Demodulator81839.7.6 RS485 Mode81839.7.7 SPI Mode81939.7.7.1 Modes of Operation81939.7.7.2 Baud Rate82039.7.7.3 Data Transfer82139.7.7.4 Receiver and Transmitter Control82239.7.7.5 Character Transmission82239.7.7.6 Character Reception82339.7.7.7 Receiver Timeout82339.7.8 LIN Mode82339.7.8.1 Modes of Operation82339.7.8.2 Baud Rate Configuration82339.7.8.3 Receiver and Transmitter Control82339.7.8.4 Character Transmission82339.7.8.5 Character Reception82339.7.8.6 Header Transmission (Master Node Configuration)82439.7.8.7 Header Reception (Slave Node Configuration)82439.7.8.8 Slave Node Synchronization82539.7.8.9 Identifier Parity82739.7.8.10 Node Action82739.7.8.11 Response Data Length82839.7.8.12 Checksum82839.7.8.13 Frame Slot Mode82839.7.8.14 LIN Errors82939.7.8.15 LIN Frame Handling83039.7.8.16 LIN Frame Handling With The DMAC83339.7.8.17 Wake-up Request83539.7.8.18 Bus Idle Time-out83539.7.9 Test Modes83639.7.9.1 Normal Mode83639.7.9.2 Automatic Echo Mode83639.7.9.3 Local Loopback Mode83739.7.9.4 Remote Loopback Mode83739.7.10 Write Protection Registers83839.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface83939.8.1 USART Control Register84039.8.2 USART Control Register (SPI_MODE)84239.8.3 USART Mode Register84439.8.4 USART Mode Register (SPI_MODE)84739.8.5 USART Interrupt Enable Register84939.8.6 USART Interrupt Enable Register (SPI_MODE)85039.8.7 USART Interrupt Enable Register (LIN_MODE)85139.8.8 USART Interrupt Disable Register85239.8.9 USART Interrupt Disable Register (SPI_MODE)85339.8.10 USART Interrupt Disable Register (LIN_MODE)85439.8.11 USART Interrupt Mask Register85539.8.12 USART Interrupt Mask Register (SPI_MODE)85639.8.13 USART Interrupt Mask Register (LIN_MODE)85739.8.14 USART Channel Status Register85839.8.15 USART Channel Status Register (SPI_MODE)86039.8.16 USART Channel Status Register (LIN_MODE)86139.8.17 USART Receive Holding Register86339.8.18 USART Transmit Holding Register86439.8.19 USART Baud Rate Generator Register86539.8.20 USART Receiver Time-out Register86639.8.21 USART Transmitter Timeguard Register86739.8.22 USART FI DI RATIO Register86839.8.23 USART Number of Errors Register86939.8.24 USART IrDA FILTER Register87039.8.25 USART Manchester Configuration Register87139.8.26 USART LIN Mode Register87339.8.27 USART LIN Identifier Register87539.8.28 USART LIN Baud Rate Register87639.8.29 USART Write Protect Mode Register87739.8.30 USART Write Protect Status Register87840. Universal Asynchronous Receiver Transmitter (UART)87940.1 Description87940.2 Embedded Characteristics87940.3 Block Diagram88040.4 Product Dependencies88140.4.1 I/O Lines88140.4.2 Power Management88140.4.3 Interrupt Source88140.5 UART Operations88140.5.1 Baud Rate Generator88140.5.2 Receiver88240.5.2.1 Receiver Reset, Enable and Disable88240.5.2.2 Start Detection and Data Sampling88240.5.2.3 Receiver Ready88340.5.2.4 Receiver Overrun88340.5.2.5 Parity Error88340.5.2.6 Receiver Framing Error88440.5.3 Transmitter88440.5.3.1 Transmitter Reset, Enable and Disable88440.5.3.2 Transmit Format88440.5.3.3 Transmitter Control88540.5.4 DMA Support88540.5.5 Test Modes88540.6 Universal Asynchronous Receiver Transmitter (UART) User Interface88740.6.1 UART Control Register88840.6.2 UART Mode Register88940.6.3 UART Interrupt Enable Register89040.6.4 UART Interrupt Disable Register89140.6.5 UART Interrupt Mask Register89240.6.6 UART Status Register89340.6.7 UART Receiver Holding Register89440.6.8 UART Transmit Holding Register89540.6.9 UART Baud Rate Generator Register89641. Controller Area Network (CAN) Programmer Datasheet89741.1 Description89741.2 Embedded Characteristics89741.3 Block Diagram89841.4 Application Block Diagram89841.5 I/O Lines Description89941.6 Product Dependencies89941.6.1 I/O Lines89941.6.2 Power Management89941.6.3 Interrupt89941.7 CAN Controller Features90041.7.1 CAN Protocol Overview90041.7.2 Mailbox Organization90041.7.2.1 Message Acceptance Procedure90041.7.2.2 Receive Mailbox90141.7.2.3 Transmit Mailbox90241.7.3 Time Management Unit90241.7.4 CAN 2.0 Standard Features90341.7.4.1 CAN Bit Timing Configuration90341.7.4.2 Error Detection90641.7.4.3 Overload90841.7.5 Low-power Mode90841.7.5.1 Enabling Low-power Mode90841.7.5.2 Disabling Low-power Mode90941.8 Functional Description91141.8.1 CAN Controller Initialization91141.8.2 CAN Controller Interrupt Handling91241.8.3 CAN Controller Message Handling91241.8.3.1 Receive Handling91241.8.3.2 Transmission Handling91641.8.3.3 Remote Frame Handling91741.8.4 CAN Controller Timing Modes91941.8.4.1 Timestamping Mode91941.8.4.2 Time Triggered Mode91941.8.5 Write Protected Registers92241.9 Controller Area Network (CAN) User Interface92341.9.1 CAN Mode Register92441.9.2 CAN Interrupt Enable Register92541.9.3 CAN Interrupt Disable Register92741.9.4 CAN Interrupt Mask Register92941.9.5 CAN Status Register93141.9.6 CAN Baudrate Register93441.9.7 CAN Timer Register93541.9.8 CAN Timestamp Register93641.9.9 CAN Error Counter Register93741.9.10 CAN Transfer Command Register93841.9.11 CAN Abort Command Register93941.9.12 CAN Write Protection Mode Register94041.9.13 CAN Write Protection Status Register94141.9.14 CAN Message Mode Register94241.9.15 CAN Message Acceptance Mask Register94341.9.16 CAN Message ID Register94441.9.17 CAN Message Family ID Register94541.9.18 CAN Message Status Register94641.9.19 CAN Message Data Low Register94941.9.20 CAN Message Data High Register95041.9.21 CAN Message Control Register95142. Analog-to-Digital Converter (ADC)95342.1 Description95342.2 Embedded Characteristics95342.3 Block Diagram95442.4 Signal Description95442.5 Product Dependencies95542.5.1 Power Management95542.5.2 Interrupt Sources95542.5.3 Analog Inputs95542.5.4 I/O Lines95542.5.5 Timer Triggers95542.5.6 Conversion Performances95542.6 Functional Description95642.6.1 Analog-to-digital Conversion95642.6.2 Conversion Reference95642.6.3 Conversion Resolution95642.6.4 Conversion Results95742.6.5 Conversion Triggers95942.6.6 Sleep Mode and Conversion Sequencer95942.6.7 Comparison Window96042.6.8 ADC Timings96042.6.9 Buffer Structure96042.6.10 Write Protected Registers96142.7 Analog-to-Digital Converter (ADC) User Interface96242.7.1 ADC Control Register96342.7.2 ADC Mode Register96442.7.3 ADC Channel Sequence 1 Register96642.7.4 ADC Channel Sequence 2 Register96742.7.5 ADC Channel Enable Register96842.7.6 ADC Channel Disable Register96942.7.7 ADC Channel Status Register97042.7.8 ADC Last Converted Data Register97142.7.9 ADC Interrupt Enable Register97242.7.10 ADC Interrupt Disable Register97342.7.11 ADC Interrupt Mask Register97442.7.12 ADC Interrupt Status Register97542.7.13 ADC Overrun Status Register97642.7.14 ADC Extended Mode Register97742.7.15 ADC Compare Window Register97842.7.16 ADC Channel Data Register97942.7.17 ADC Trigger Register98042.7.18 ADC Write Protect Mode Register98142.7.19 ADC Write Protect Status Register98243. Software Modem Device (SMD)98343.1 Description98343.2 Embedded Characteristics98443.3 Block Diagram98444. Synchronous Serial Controller (SSC)98544.1 Description98544.2 Embedded Characteristics98544.3 Block Diagram98644.4 Application Block Diagram98644.5 Pin Name List98744.6 Product Dependencies98744.6.1 I/O Lines98744.6.2 Power Management98744.6.3 Interrupt98744.7 Functional Description98844.7.1 Clock Management98944.7.1.1 Clock Divider98944.7.1.2 Transmitter Clock Management99044.7.1.3 Receiver Clock Management99044.7.1.4 Serial Clock Ratio Considerations99144.7.2 Transmitter Operations99144.7.3 Receiver Operations99244.7.4 Start99344.7.5 Frame Sync99544.7.5.1 Frame Sync Data99544.7.5.2 Frame Sync Edge Detection99544.7.6 Receive Compare Modes99544.7.6.1 Compare Functions99544.7.7 Data Format99644.7.8 Loop Mode99744.7.9 Interrupt99744.8 SSC Application Examples99944.8.1 Write Protection Registers100144.9 Synchronous Serial Controller (SSC) User Interface100244.9.1 SSC Control Register100344.9.2 SSC Clock Mode Register100444.9.3 SSC Receive Clock Mode Register100544.9.4 SSC Receive Frame Mode Register100744.9.5 SSC Transmit Clock Mode Register100944.9.6 SSC Transmit Frame Mode Register101144.9.7 SSC Receive Holding Register101344.9.8 SSC Transmit Holding Register101344.9.9 SSC Receive Synchronization Holding Register101444.9.10 SSC Transmit Synchronization Holding Register101444.9.11 SSC Receive Compare 0 Register101544.9.12 SSC Receive Compare 1 Register101544.9.13 SSC Status Register101644.9.14 SSC Interrupt Enable Register101844.9.15 SSC Interrupt Disable Register101944.9.16 SSC Interrupt Mask Register102044.9.17 SSC Write Protect Mode Register102144.9.18 SSC Write Protect Status Register102245. Ethernet MAC 10/100 (EMAC)102345.1 Description102345.2 Embedded Characteristics102345.3 Block Diagram102445.4 Functional Description102545.4.1 Clock102545.4.2 Memory Interface102545.4.2.1 FIFO102645.4.2.2 Receive Buffers102645.4.2.3 Transmit Buffer102845.4.3 Transmit Block102945.4.4 Pause Frame Support103045.4.5 Receive Block103045.4.6 Address Checking Block103045.4.7 Broadcast Address103145.4.8 Hash Addressing103245.4.9 Copy All Frames (or Promiscuous Mode)103245.4.10 Type ID Checking103245.4.11 VLAN Support103245.4.12 PHY Maintenance103345.4.13 Physical Interface103345.4.13.1 RMII Transmit and Receive Operation103445.5 Programming Interface103445.5.1 Initialization103445.5.1.1 Configuration103445.5.1.2 Receive Buffer List103445.5.1.3 Transmit Buffer List103545.5.1.4 Address Matching103545.5.1.5 Interrupts103545.5.1.6 Transmitting Frames103545.5.1.7 Receiving Frames103645.6 Ethernet MAC 10/100 (EMAC) User Interface103745.6.1 Network Control Register103945.6.2 Network Configuration Register104145.6.3 Network Status Register104345.6.4 Transmit Status Register104445.6.5 Receive Buffer Queue Pointer Register104545.6.6 Transmit Buffer Queue Pointer Register104645.6.7 Receive Status Register104745.6.8 Interrupt Status Register104845.6.9 Interrupt Enable Register105045.6.10 Interrupt Disable Register105245.6.11 Interrupt Mask Register105445.6.12 PHY Maintenance Register105645.6.13 Pause Time Register105745.6.14 Hash Register Bottom105845.6.15 Hash Register Top105945.6.16 Specific Address 1 Bottom Register106045.6.17 Specific Address 1 Top Register106145.6.18 Specific Address 2 Bottom Register106245.6.19 Specific Address 2 Top Register106345.6.20 Specific Address 3 Bottom Register106445.6.21 Specific Address 3 Top Register106545.6.22 Specific Address 4 Bottom Register106645.6.23 Specific Address 4 Top Register106745.6.24 Type ID Checking Register106845.6.25 User Input/Output Register106945.6.26 EMAC Statistic Registers107045.6.26.1 Pause Frames Received Register107145.6.26.2 Frames Transmitted OK Register107245.6.26.3 Single Collision Frames Register107345.6.26.4 Multicollision Frames Register107445.6.26.5 Frames Received OK Register107545.6.26.6 Frames Check Sequence Errors Register107645.6.26.7 Alignment Errors Register107745.6.26.8 Deferred Transmission Frames Register107845.6.26.9 Late Collisions Register107945.6.26.10 Excessive Collisions Register108045.6.26.11 Transmit Underrun Errors Register108145.6.26.12 Carrier Sense Errors Register108245.6.26.13 Receive Resource Errors Register108345.6.26.14 Receive Overrun Errors Register108445.6.26.15 Receive Symbol Errors Register108545.6.26.16 Excessive Length Errors Register108645.6.26.17 Receive Jabbers Register108745.6.26.18 Undersize Frames Register108845.6.26.19 SQE Test Errors Register108945.6.26.20 Received Length Field Mismatch Register109046. Electrical Characteristics109146.1 Absolute Maximum Ratings109146.2 DC Characteristics109246.3 Power Consumption109346.3.1 Power Consumption versus Modes109346.4 Clock Characteristics109546.4.1 Processor Clock Characteristics109546.4.2 Master Clock Characteristics109546.5 Main Oscillator Characteristics109546.5.1 Crystal Oscillator Characteristics109646.5.2 XIN Clock Characteristics109646.6 12 MHz RC Oscillator Characteristics109746.7 32 kHz Oscillator Characteristics109746.7.1 32 kHz Crystal Characteristics109846.7.2 XIN32 Clock Characteristics109846.8 32 kHz RC Oscillator Characteristics109846.9 PLL Characteristics109946.9.1 UTMI PLL Characteristics109946.10 I/Os110046.11 USB HS Characteristics110046.12 USB Transceiver Characteristics110146.13 Analog-to-Digital Converter (ADC)110246.14 POR Characteristics110346.14.1 Core Power Supply POR Characteristics110346.14.2 Backup Power Supply POR Characteristics110346.15 Power Sequence Requirements110446.15.1 Power-Up Sequence110446.16 SMC Timings110546.16.1 Timing Conditions110546.16.2 Timing Extraction110546.16.2.1 Zero Hold Mode Restrictions110546.16.2.2 Read Timings110646.16.2.3 Write Timings110746.17 DDRSDRC Timings110846.18 Peripheral Timings110946.18.1 SPI110946.18.1.1 Maximum SPI Frequency110946.18.1.2 Timing Conditions110946.18.1.3 Timing Extraction110946.18.2 SSC111346.18.2.1 Timing conditions111346.18.2.2 Timing Extraction111346.18.3 HSMCI111746.18.4 EMAC111746.18.4.1 Timing conditions111746.18.4.2 Timing constraints111746.18.4.3 MII Mode111846.18.4.4 RMII Mode111946.18.5 USART in SPI Mode Timings112046.18.5.1 Timing conditions112046.18.5.2 Timing extraction112046.19 Two-wire Interface Characteristics112347. Mechanical Overview112547.1 217-ball BGA Package112547.2 Marking112648. SAM9X25 Ordering Information112749. SAM9X25 Errata112849.1 External Bus Interface (EBI)112849.1.1 EBI: Data lines are Hi-Z after reset112849.2 Reset Controller (RSTC)112849.2.1 RSTC: Reset during SDRAM Accesses112849.2.2 Static Memory Controller (SMC)112849.2.3 SMC: SMC DELAY I/O Registers are write-only112849.3 USB High Speed Host Port (UHPHS) and Device Port (UDPHS)112849.3.1 UHPHS/UDPHS: Bad Lock of the USB High speed transceiver DLL112849.4 Timer Counter (TC)112949.4.1 TC: The TIOA5 signal is not well connected112949.5 Boot Strategy112949.5.1 NAND Flash Boot Detection using ONFI parameters does not work112949.6 Real Time Clock (RTC)113049.6.1 RTC: Interrupt Mask Register cannot be used1130Revision History1131Table of Contents1143Dimensioni: 4,89 MBPagine: 1151Language: EnglishApri il manuale
