Scheda Tecnica (AT32UC3L0-XPLD)Sommario1. Related Items32. General Information42.1 Preprogrammed Firmware52.2 Power Supply62.3 Measuring the AT32UC3L064 Power Consumption62.4 Programming the AT32UC3L064 through the UART-to-USB Gateway62.5 Communication through the UART-to-USB Gateway63. Connectors73.1 Programming Headers73.2 I/O Expansion Headers74. Memories105. Miscellaneous I/O115.1 Mechanical Switch115.2 LEDs115.3 Analog I/O115.4 Touch125.5 Board Controller126. Included Code Example136.1 Compiling and Running137. Schematics148. Known Issues218.1 Light Sensor218.2 USB Test Points219. Revision History229.1 Revision 42210. EVALUATION BOARD/KIT IMPORTANT NOTICE2311. Document Revision History24Dimensioni: 797 KBPagine: 25Language: EnglishApri il manuale
Scheda Tecnica (AT32UC3L0-XPLD)SommarioFeatures11. Description32. Overview52.1 Block Diagram52.2 Configuration Summary63. Package and Pinout73.1 Package73.2 Peripheral Multiplexing on I/O lines93.2.1 Multiplexed signals93.2.1.1 TWI, 5V Tolerant, and SMBUS Pins103.2.2 Peripheral Functions113.2.3 JTAG Port Connections113.2.4 Nexus OCD AUX Port Connections113.2.5 Oscillator Pinout123.2.6 Other Functions123.3 Signal Descriptions133.4 I/O Line Considerations163.4.1 JTAG Pins163.4.2 PA00163.4.3 RESET_N Pin163.4.4 TWI Pins PA21/PB04/PB05163.4.5 TWI Pins PA05/PA07/PA17163.4.6 GPIO Pins163.4.7 High-Drive Pins163.4.8 RC32OUT Pin173.4.8.1 Clock output at startup173.4.8.2 XOUT32_2 function173.4.9 ADC Input Pins174. Processor and Architecture184.1 Features184.2 AVR32 Architecture184.3 The AVR32UC CPU194.3.1 Pipeline Overview204.3.2 AVR32A Microarchitecture Compliance214.3.2.1 Interrupt Handling214.3.2.2 Java Support214.3.2.3 Memory Protection214.3.2.4 Unaligned Reference Handling214.3.2.5 Unimplemented Instructions224.3.2.6 CPU and Architecture Revision224.4 Programming Model234.4.1 Register File Configuration234.4.2 Status Register Configuration234.4.3 Processor States244.4.3.1 Normal RISC State244.4.3.2 Debug State244.4.3.3 Secure State254.4.4 System Registers254.5 Exceptions and Interrupts274.5.1 System Stack Issues284.5.2 Exceptions and Interrupt Requests284.5.3 Supervisor Calls294.5.4 Debug Requests294.5.5 Entry Points for Events295. Memories325.1 Embedded Memories325.2 Physical Memory Map325.3 Peripheral Address Map335.4 CPU Local Bus Mapping346. Supply and Startup Considerations366.1 Supply Considerations366.1.1 Power Supplies366.1.2 Voltage Regulator366.1.3 Regulator Connection366.1.3.1 3.3 V Single Supply Mode376.1.3.2 1.8 V Single Supply Mode386.1.3.3 3.3 V Supply Mode with 1.8 V Regulated I/O Lines396.1.4 Power-up Sequence406.1.4.1 Maximum Rise Rate406.1.4.2 Minimum Rise Rate406.2 Startup Considerations406.2.1 Starting of Clocks406.2.2 Fetching of Initial Instructions407. Electrical Characteristics417.1 Disclaimer417.2 Absolute Maximum Ratings*417.3 Supply Characteristics417.4 Maximum Clock Frequencies427.5 Power Consumption427.5.1 Peripheral Power Consumption457.6 I/O Pin Characteristics477.7 Oscillator Characteristics507.7.1 Oscillator 0 (OSC0) Characteristics507.7.1.1 Digital Clock Characteristics507.7.1.2 Crystal Oscillator Characteristics507.7.2 32 KHz Crystal Oscillator (OSC32K) Characteristics517.7.3 Digital Frequency Locked Loop (DFLL) Characteristics527.7.4 120 MHz RC Oscillator (RC120M) Characteristics537.7.5 32 kHz RC Oscillator (RC32K) Characteristics547.7.6 System RC Oscillator (RCSYS) Characteristics547.8 Flash Characteristics547.9 Analog Characteristics557.9.1 Voltage Regulator Characteristics557.9.2 Power-on Reset 18 Characteristics567.9.3 Power-on Reset 33 Characteristics577.9.4 Brown Out Detector Characteristics577.9.5 Supply Monitor 33 Characteristics587.9.6 Analog to Digital Converter Characteristics597.9.6.1 Inputs and Sample and Hold Aquisition Time597.9.6.2 Applicable Conditions and Derating Data607.9.7 Temperature Sensor Characteristics617.9.8 Analog Comparator Characteristics617.9.9 Capacitive Touch Characteristics627.9.9.1 Discharge Current Source627.9.9.2 Strong Pull-up Pull-down627.10 Timing Characteristics637.10.1 Startup, Reset, and Wake-up Timing637.10.2 RESET_N Timing637.10.3 USART in SPI Mode Timing647.10.3.1 Master mode647.10.3.2 Slave mode657.10.4 SPI Timing677.10.4.1 Master mode677.10.4.2 Slave mode687.10.5 TWIM/TWIS Timing707.10.6 JTAG Timing728. Mechanical Characteristics738.1 Thermal Considerations738.1.1 Thermal Data738.1.2 Junction Temperature738.2 Package Drawings748.3 Soldering Profile779. Ordering Information7810. Errata7910.1 Rev. E7910.1.1 Processor and Architecture7910.1.2 FLASHCDW7910.1.3 Power Manager7910.1.4 SCIF8010.1.5 AST8010.1.6 WDT8110.1.7 GPIO8110.1.8 SPI8110.1.9 TWI8210.1.10 ADCIFB8310.1.11 CAT8310.1.12 aWire8310.1.13 CHIP8310.1.14 I/O Pins8410.2 Rev. D8410.2.1 Processor and Architecture8410.2.2 FLASHCDW8410.2.3 Power Manager8410.2.4 SCIF8510.2.5 AST8610.2.6 WDT8610.2.7 GPIO8710.2.8 SPI8710.2.9 TWI8810.2.10 ADCIFB8810.2.11 CAT8910.2.12 aWire8910.2.13 CHIP8910.2.14 I/O Pins9010.3 Rev. C9010.4 Rev. B9010.4.1 Processor and Architecture9010.4.2 PDCA9010.4.3 FLASHCDW9110.4.4 SAU9110.4.5 HMATRIX9210.4.6 Power Manager9210.4.7 SCIF9310.4.8 AST9610.4.9 WDT9610.4.10 FREQM9610.4.11 GPIO9710.4.12 USART9710.4.13 SPI9710.4.14 TWI9810.4.15 PWMA9910.4.16 TC10010.4.17 ADCIFB10010.4.18 ACIFB10110.4.19 CAT10110.4.20 GLOC10210.4.21 aWire10210.4.22 Chip10310.4.23 I/O Pins10410.510411. Datasheet Revision History10511.1 Rev. G - 06/201110511.2 Rev. F- 11/201010511.3 Rev. E- 10/201010511.4 Rev. D - 06/201010611.5 Rev. C - 06/201010611.6 Rev. B - 05/201010611.7 Rev. A – 06/2009107Table of Contents108Dimensioni: 1,92 MBPagine: 110Language: EnglishApri il manuale
