Manuali utente per Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO

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ATSAMD20-XPRO

Scheda Tecnica (English)Scheda Tecnica (English)

Scheda Tecnica (ATSAMD20-XPRO)

Sommario

Scheda Tecnica (ATSAMD20-XPRO)

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671 KB
Pagine:

16
Language:

English

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Scheda Tecnica (ATSAMD20-XPRO)

Sommario

Description
1
Features
2
1. Configuration Summary
3
2. Ordering Information
4
- 2.1 SAM D20E
  4
- 2.2 SAM D20G
  5
- 2.3 SAM D20J
  6
3. Block Diagram
7
4. Pinout
8
- 4.1 SAM D20J
  8
- 4.2 SAM D20G
  9
- 4.3 SAM D20E
  10
5. I/O Multiplexing and Considerations
11
- 5.1 Multiplexed Signals
  11
- 5.2 Other Functions
  13
  - 5.2.1 Oscillator Pinout
    13
  - 5.2.2 Serial Wire Debug Interface Pinout
    13
6. Signal Descriptions List
14
7. Power Supply and Start-Up Considerations
16
- 7.1 Power Domain Overview
  16
- 7.2 Power Supply Considerations
  16
- 7.3 Power-Up
  18
- 7.4 Power-On Reset and Brown-Out Detector
  18
8. Product Mapping
19
9. Memories
20
- 9.1 Embedded Memories
  20
- 9.2 Physical Memory Map
  20
- 9.3 Non-Volatile Memory (NVM) User Row Mapping
  22
- 9.4 NVM Software Calibration Area Mapping
  23
- 9.5 Serial Number
  23
10. Processor and Architecture
24
- 10.1 Cortex-M0+ Processor
  24
- 10.2 Nested Vector Interrupt Controller
  25
  - 10.2.1 Overview
    25
  - 10.2.2 Interrupt Line Mapping
    25
- 10.3 High-Speed Bus Matrix
  26
  - 10.3.1 Features
    26
  - 10.3.2 Configuration
    27
- 10.4 AHB-APB Bridge
  28
- 10.5 PAC – Peripheral Access Controller
  28
  - 10.5.1 Overview
    28
- 10.6 Register Description
  29
11. Peripherals Configuration Overview
35
12. DSU – Device Service Unit
37
- 12.1 Overview
  37
- 12.2 Features
  37
- 12.3 Block Diagram
  37
- 12.4 Signal Description
  38
- 12.5 Product Dependencies
  38
  - 12.5.1 I/O Lines
    38
  - 12.5.2 Power Management
    38
  - 12.5.3 Clocks
    38
  - 12.5.4 Interrupts
    38
  - 12.5.5 Events
    38
  - 12.5.6 Register Access Protection
    38
  - 12.5.7 Analog Connections
    38
- 12.6 Debug Operation
  39
- 12.7 Chip-Erase
  40
- 12.8 Programming
  40
- 12.9 Intellectual Property Protection
  41
- 12.10 Device Identification
  42
  - 12.10.1 CoreSight Identification
    42
  - 12.10.2 DSU Chip Identification Method:
    43
- 12.11 Functional Description
  43
- 12.12 Register Summary
  48
- 12.13 Register Description
  51
13. Clock System
73
- 13.1 Clock Distribution
  73
- 13.2 Synchronous and Asynchronous Clocks
  74
- 13.3 Register Synchronization
  74
- 13.4 Enabling a Peripheral
  77
- 13.5 On-demand, Clock Requests
  77
- 13.6 Power Consumption vs Speed
  78
- 13.7 Clocks after Reset
  78
14. GCLK – Generic Clock Controller
79
- 14.1 Overview
  79
- 14.2 Features
  79
- 14.3 Block Diagram
  79
- 14.4 Signal Description
  80
- 14.5 Product Dependencies
  80
  - 14.5.1 I/O Lines
    80
  - 14.5.2 Power Management
    80
  - 14.5.3 Clocks
    80
  - 14.5.4 Interrupts
    81
  - 14.5.5 Events
    81
  - 14.5.6 Debug Operation
    81
  - 14.5.7 Register Access Protection
    81
  - 14.5.8 Analog Connections
    81
- 14.6 Functional Description
  81
- 14.7 Register Summary
  86
- 14.8 Register Description
  87
15. PM – Power Manager
101
- 15.1 Overview
  101
- 15.2 Features
  101
- 15.3 Block Diagram
  102
- 15.4 Signal Description
  102
- 15.5 Product Dependencies
  102
  - 15.5.1 I/O Lines
    102
  - 15.5.2 Power Management
    102
  - 15.5.3 Clocks
    103
    - 15.5.3.1 Main Clock
      103
    - 15.5.3.2 CPU Clock
      103
    - 15.5.3.3 AHB Clock
      103
    - 15.5.3.4 APBx Clocks
      103
  - 15.5.4 Interrupts
    103
  - 15.5.5 Events
    103
  - 15.5.6 Debug Operation
    103
  - 15.5.7 Register Access Protection
    103
  - 15.5.8 Analog Connections
    103
- 15.6 Functional Description
  104
- 15.7 Register Summary
  111
- 15.8 Register Description
  113
  - 15.8.1 Control
    114
  - 15.8.2 Sleep Mode
    115
  - 15.8.3 CPU Clock Select
    116
  - 15.8.4 APBA Clock Select
    117
  - 15.8.5 APBB Clock Select
    118
  - 15.8.6 APBC Clock Select
    119
  - 15.8.7 AHB Mask
    120
  - 15.8.8 APBA Mask
    121
  - 15.8.9 APBB Mask
    122
  - 15.8.10 APBC Mask
    123
  - 15.8.11 Interrupt Enable Clear
    124
  - 15.8.12 Interrupt Enable Set
    125
  - 15.8.13 Interrupt Flag Status and Clear
    126
  - 15.8.14 Reset Cause
    127
16. SYSCTRL – System Controller
128
- 16.1 Overview
  128
- 16.2 Features
  128
- 16.3 Block Diagram
  129
- 16.4 Signal Description
  129
- 16.5 Product Dependencies
  130
  - 16.5.1 I/O Lines
    130
  - 16.5.2 Power Management
    130
  - 16.5.3 Clocks
    130
  - 16.5.4 Interrupts
    130
  - 16.5.5 Debug Operation
    130
  - 16.5.6 Register Access Protection
    130
  - 16.5.7 Analog Connections
    130
- 16.6 Functional Description
  131
- 16.7 Register Summary
  140
- 16.8 Register Description
  142
17. WDT – Watchdog Timer
177
- 17.1 Overview
  177
- 17.2 Features
  177
- 17.3 Block Diagram
  177
- 17.4 Signal Description
  178
- 17.5 Product Dependencies
  178
  - 17.5.1 I/O Lines
    178
  - 17.5.2 Power Management
    178
  - 17.5.3 Clocks
    178
  - 17.5.4 DMA
    178
  - 17.5.5 Interrupts
    178
  - 17.5.6 Events
    178
  - 17.5.7 Debug Operation
    178
  - 17.5.8 Register Access Protection
    179
  - 17.5.9 Analog Connections
    179
- 17.6 Functional Description
  179
  - 17.6.1 Principle of Operation
    179
  - 17.6.2 Basic Operation
    179
    - 17.6.2.1 Initialization
      179
    - 17.6.2.2 Configurable Reset Values
      180
    - 17.6.2.3 Enabling and Disabling
      180
    - 17.6.2.4 Normal Mode
      180
    - 17.6.2.5 Window Mode
      181
  - 17.6.3 Additional Features
    182
    - 17.6.3.1 Always-On Mode
      182
  - 17.6.4 Interrupts
    182
  - 17.6.5 Synchronization
    183
- 17.7 Register Summary
  184
- 17.8 Register Description
  185
  - 17.8.1 Control
    186
  - 17.8.2 Configuration
    187
  - 17.8.3 Early Warning Interrupt Control
    189
  - 17.8.4 Interrupt Enable Clear
    190
  - 17.8.5 Interrupt Enable Set
    191
  - 17.8.6 Interrupt Flag Status and Clear
    192
  - 17.8.7 Status
    193
  - 17.8.8 Clear
    194
18. RTC – Real-Time Counter
195
- 18.1 Overview
  195
- 18.2 Features
  195
- 18.3 Block Diagram
  195
- 18.4 Signal Description
  196
- 18.5 Product Dependencies
  196
  - 18.5.1 I/O Lines
    196
  - 18.5.2 Power Management
    196
  - 18.5.3 Clocks
    197
  - 18.5.4 DMA
    197
  - 18.5.5 Interrupts
    197
  - 18.5.6 Events
    197
  - 18.5.7 Debug Operation
    197
  - 18.5.8 Register Access Protection
    197
  - 18.5.9 Analog Connections
    197
- 18.6 Functional Description
  198
  - 18.6.1 Principle of Operation
    198
  - 18.6.2 Basic Operation
    198
    - 18.6.2.1 Initialization
      198
    - 18.6.2.2 Enabling, Disabling and Resetting
      198
  - 18.6.3 Operating Modes
    199
  - 18.6.4 Additional Features
    200
    - 18.6.4.1 Periodic Events
      200
    - 18.6.4.2 Frequency Correction
      200
  - 18.6.5 DMA Operation
    201
  - 18.6.6 Interrupts
    201
  - 18.6.7 Events
    201
  - 18.6.8 Sleep Mode Operation
    201
  - 18.6.9 Synchronization
    202
- 18.7 Register Summary
  203
- 18.8 Register Description
  206
  - 18.8.1 Control
    207
    - 18.8.1.1 Mode 0
      207
    - 18.8.1.2 Mode 1
      209
    - 18.8.1.3 Mode 2
      211
  - 18.8.2 Read Request
    213
  - 18.8.3 Event Control
    214
    - 18.8.3.1 Mode 0
      214
    - 18.8.3.2 Mode 1
      215
    - 18.8.3.3 Mode 2
      216
  - 18.8.4 Interrupt Enable Clear
    217
    - 18.8.4.1 Mode 0
      217
    - 18.8.4.2 Mode 1
      218
    - 18.8.4.3 Mode 2
      219
  - 18.8.5 Interrupt Enable Set
    220
    - 18.8.5.1 Mode 0
      220
    - 18.8.5.2 Mode 1
      221
    - 18.8.5.3 Mode 2
      222
  - 18.8.6 Interrupt Flag Status and Clear
    223
    - 18.8.6.1 Mode 0
      223
    - 18.8.6.2 Mode 1
      224
    - 18.8.6.3 Mode 2
      225
  - 18.8.7 Status
    226
  - 18.8.8 Debug Control
    227
  - 18.8.9 Frequency Correction
    228
  - 18.8.10 Counter Value
    229
    - 18.8.10.1 Mode 0
      229
    - 18.8.10.2 Mode 1
      230
  - 18.8.11 Clock Value
    231
    - 18.8.11.1 Mode 2
      231
  - 18.8.12 Counter Period
    233
    - 18.8.12.1 Mode 1
      233
  - 18.8.13 Compare n Value
    234
    - 18.8.13.1 Mode 0
      234
    - 18.8.13.2 Mode 1
      235
  - 18.8.14 Alarm n Value
    236
    - 18.8.14.1 Mode 2
      236
  - 18.8.15 Alarm n Mask
    238
    - 18.8.15.1 Mode 2
      238
19. EIC – External Interrupt Controller
239
- 19.1 Overview
  239
- 19.2 Features
  239
- 19.3 Block Diagram
  239
- 19.4 Signal Description
  240
- 19.5 Product Dependencies
  240
  - 19.5.1 I/O Lines
    240
  - 19.5.2 Power Management
    240
  - 19.5.3 Clocks
    240
  - 19.5.4 Interrupts
    240
  - 19.5.5 Events
    240
  - 19.5.6 Debug Operation
    241
  - 19.5.7 Register Access Protection
    241
  - 19.5.8 Analog Connections
    241
- 19.6 Functional Description
  241
  - 19.6.1 Principle of Operation
    241
  - 19.6.2 Basic Operation
    241
    - 19.6.2.1 Initialization
      241
    - 19.6.2.2 Enabling, Disabling and Resetting
      241
  - 19.6.3 External Pin Processing
    241
  - 19.6.4 Additional Features
    243
  - 19.6.5 Interrupts
    243
  - 19.6.6 Events
    243
  - 19.6.7 Sleep Mode Operation
    244
  - 19.6.8 Synchronization
    244
- 19.7 Register Summary
  245
- 19.8 Register Description
  246
  - 19.8.1 Control
    247
  - 19.8.2 Status
    248
  - 19.8.3 Non-Maskable Interrupt Control
    249
  - 19.8.4 Non-Maskable Interrupt Flag Status and Clear
    250
  - 19.8.5 Event Control
    251
  - 19.8.6 Interrupt Enable Clear
    252
  - 19.8.7 Interrupt Enable Set
    253
  - 19.8.8 Interrupt Flag Status and Clear
    254
  - 19.8.9 Wake-Up Enable
    255
  - 19.8.10 Configuration n
    256
20. NVMCTRL – Non-Volatile Memory Controller
258
- 20.1 Overview
  258
- 20.2 Features
  258
- 20.3 Block Diagram
  258
- 20.4 Signal Description
  258
- 20.5 Product Dependencies
  259
  - 20.5.1 Power Management
    259
  - 20.5.2 Clocks
    259
  - 20.5.3 Interrupts
    259
  - 20.5.4 Debug Operation
    259
  - 20.5.5 Register Access Protection
    259
  - 20.5.6 Analog Connections
    259
- 20.6 Functional Description
  259
  - 20.6.1 Principle of Operation
    259
  - 20.6.2 Basic Operations
    260
    - 20.6.2.1 Initialization
      260
    - 20.6.2.2 Enabling, Disabling and Resetting
      260
  - 20.6.3 Memory Organization
    260
  - 20.6.4 Region Lock Bits
    261
  - 20.6.5 Command and Data Interface
    261
    - 20.6.5.1 NVM Read
      262
    - 20.6.5.2 NVM Write
      262
    - 20.6.5.3 Page Buffer Clear
      263
    - 20.6.5.4 Erase Row
      263
    - 20.6.5.5 Lock and Unlock Region
      263
    - 20.6.5.6 Set and Clear Power Reduction Mode
      263
  - 20.6.6 NVM User Configuration
    263
  - 20.6.7 Security Bit
    264
  - 20.6.8 Cache
    264
- 20.7 Register Summary
  265
- 20.8 Register Description
  266
  - 20.8.1 Control A
    267
  - 20.8.2 Control B
    269
  - 20.8.3 NVM Parameter
    271
  - 20.8.4 Interrupt Enable Clear
    273
  - 20.8.5 Interrupt Enable Set
    274
  - 20.8.6 Interrupt Flag Status and Clear
    275
  - 20.8.7 Status
    276
  - 20.8.8 Address
    278
  - 20.8.9 Lock Section
    279
21. PORT
280
- 21.1 Overview
  280
- 21.2 Features
  280
- 21.3 Block Diagram
  281
- 21.4 Signal Description
  281
- 21.5 Product Dependencies
  281
  - 21.5.1 I/O Lines
    281
  - 21.5.2 Power Management
    282
  - 21.5.3 Clocks
    282
  - 21.5.4 DMA
    282
  - 21.5.5 Interrupts
    282
  - 21.5.6 Events
    282
  - 21.5.7 Debug Operation
    282
  - 21.5.8 Register Access Protection
    282
  - 21.5.9 Analog Connections
    282
  - 21.5.10 CPU Local Bus
    282
- 21.6 Functional Description
  283
- 21.7 Register Summary
  288
- 21.8 Register Description
  290
  - 21.8.1 Data Direction
    291
  - 21.8.2 Data Direction Clear
    292
  - 21.8.3 Data Direction Set
    293
  - 21.8.4 Data Direction Toggle
    294
  - 21.8.5 Data Output Value
    295
  - 21.8.6 Data Output Value Clear
    296
  - 21.8.7 Data Output Value Set
    297
  - 21.8.8 Data Output Value Toggle
    298
  - 21.8.9 Data Input Value
    299
  - 21.8.10 Control
    300
  - 21.8.11 Write Configuration
    301
  - 21.8.12 Peripheral Multiplexing n
    304
  - 21.8.13 Pin Configuration y
    305
22. EVSYS – Event System
306
- 22.1 Overview
  306
- 22.2 Features
  306
- 22.3 Block Diagram
  307
- 22.4 Signal Description
  307
- 22.5 Product Dependencies
  307
  - 22.5.1 I/O Lines
    307
  - 22.5.2 Power Management
    307
  - 22.5.3 Clocks
    308
  - 22.5.4 DMA
    308
  - 22.5.5 Interrupts
    308
  - 22.5.6 Events
    308
  - 22.5.7 Debug Operation
    308
  - 22.5.8 Register Access Protection
    308
  - 22.5.9 Analog Connections
    308
- 22.6 Functional Description
  308
  - 22.6.1 Principle of Operation
    308
  - 22.6.2 Basic Operation
    308
    - 22.6.2.1 Initialization
      308
    - 22.6.2.2 Enabling, Disabling and Resetting
      309
    - 22.6.2.3 User Multiplexer Setup
      309
    - 22.6.2.4 Channel Setup
      309
    - 22.6.2.5 Channel Path
      310
    - 22.6.2.6 Edge Detection
      311
    - 22.6.2.7 Channel Status
      311
    - 22.6.2.8 Software Event
      311
  - 22.6.3 Interrupts
    311
    - 22.6.3.1 The Overrun Channel x Interrupt
      312
    - 22.6.3.2 The Event Detected Channel x Interrupt
      312
  - 22.6.4 Sleep Mode Operation
    312
- 22.7 Register Summary
  313
- 22.8 Register Description
  314
  - 22.8.1 Control
    314
  - 22.8.2 Channel
    315
  - 22.8.3 User Multiplexer
    320
  - 22.8.4 Channel Status
    322
  - 22.8.5 Interrupt Enable Clear
    323
  - 22.8.6 Interrupt Enable Set
    325
  - 22.8.7 Interrupt Flag Status and Clear
    327
23. SERCOM – Serial Communication Interface
329
- 23.1 Overview
  329
- 23.2 Features
  329
- 23.3 Block Diagram
  329
- 23.4 Signal Description
  329
- 23.5 Product Dependencies
  330
  - 23.5.1 I/O Lines
    330
  - 23.5.2 Power Management
    330
  - 23.5.3 Clocks
    330
  - 23.5.4 DMA
    330
  - 23.5.5 Interrupts
    330
  - 23.5.6 Events
    330
  - 23.5.7 Debug Operation
    330
  - 23.5.8 Register Access Protection
    331
  - 23.5.9 Analog Connections
    331
- 23.6 Functional Description
  331
  - 23.6.1 Principle of Operation
    331
  - 23.6.2 Basic Operation
    332
  - 23.6.3 Additional Features
    335
    - 23.6.3.1 Address Match and Mask
      335
  - 23.6.4 DMA Operation
    335
  - 23.6.5 Interrupts
    336
  - 23.6.6 Events
    336
  - 23.6.7 Sleep Mode Operation
    336
  - 23.6.8 Synchronization
    336
24. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter
337
- 24.1 Overview
  337
- 24.2 Features
  337
- 24.3 Block Diagram
  338
- 24.4 Signal Description
  338
- 24.5 Product Dependencies
  338
  - 24.5.1 I/O Lines
    338
  - 24.5.2 Power Management
    339
  - 24.5.3 Clocks
    339
  - 24.5.4 DMA
    339
  - 24.5.5 Interrupts
    339
  - 24.5.6 Events
    339
  - 24.5.7 Debug Operation
    339
  - 24.5.8 Register Access Protection
    339
  - 24.5.9 Analog Connections
    340
- 24.6 Functional Description
  340
  - 24.6.1 Principle of Operation
    340
  - 24.6.2 Basic Operation
    340
  - 24.6.3 Additional Features
    344
    - 24.6.3.1 Parity
      344
    - 24.6.3.2 Loop-back Mode
      344
    - 24.6.3.3 Start-of-Frame Detection
      345
  - 24.6.4 Interrupts
    345
  - 24.6.5 Events
    345
  - 24.6.6 Sleep Mode Operation
    345
  - 24.6.7 Synchronization
    345
- 24.7 Register Summary
  347
- 24.8 Register Description
  348
  - 24.8.1 Control A
    348
  - 24.8.2 Control B
    352
  - 24.8.3 Debug Control
    355
  - 24.8.4 Baud
    356
  - 24.8.5 Interrupt Enable Clear
    357
  - 24.8.6 Interrupt Enable Set
    358
  - 24.8.7 Interrupt Flag Status and Clear
    359
  - 24.8.8 Status
    360
  - 24.8.9 Data
    361
25. SERCOM SPI – SERCOM Serial Peripheral Interface
362
- 25.1 Overview
  362
- 25.2 Features
  362
- 25.3 Block Diagram
  362
- 25.4 Signal Description
  362
- 25.5 Product Dependencies
  363
  - 25.5.1 I/O Lines
    363
  - 25.5.2 Power Management
    363
  - 25.5.3 Clocks
    363
  - 25.5.4 DMA
    363
  - 25.5.5 Interrupts
    363
  - 25.5.6 Events
    363
  - 25.5.7 Debug Operation
    364
  - 25.5.8 Register Access Protection
    364
  - 25.5.9 Analog Connections
    364
- 25.6 Functional Description
  364
  - 25.6.1 Principle of Operation
    364
  - 25.6.2 Basic Operation
    365
    - 25.6.2.1 Initialization
      365
    - 25.6.2.2 Enabling, Disabling and Resetting
      365
    - 25.6.2.3 Clock Generation
      365
    - 25.6.2.4 Data Register
      365
    - 25.6.2.5 SPI Transfer Modes
      365
    - 25.6.2.6 Transferring Data
      367
    - 25.6.2.7 Receiver Error Bit
      367
  - 25.6.3 Additional Features
    368
  - 25.6.4 Interrupts
    369
  - 25.6.5 Events
    370
  - 25.6.6 Sleep Mode Operation
    370
  - 25.6.7 Synchronization
    370
- 25.7 Register Summary
  371
- 25.8 Register Description
  372
  - 25.8.1 Control A
    373
  - 25.8.2 Control B
    377
  - 25.8.3 Debug Control
    379
  - 25.8.4 Baud Rate
    380
  - 25.8.5 Interrupt Enable Clear
    381
  - 25.8.6 Interrupt Enable Set
    382
  - 25.8.7 Interrupt Flag Status and Clear
    383
  - 25.8.8 Status
    384
  - 25.8.9 Address
    385
  - 25.8.10 Data
    386
26. SERCOM I2C – SERCOM Inter-Integrated Circuit
387
- 26.1 Overview
  387
- 26.2 Features
  387
- 26.3 Block Diagram
  387
- 26.4 Signal Description
  388
- 26.5 Product Dependencies
  388
  - 26.5.1 I/O Lines
    388
  - 26.5.2 Power Management
    388
  - 26.5.3 Clocks
    388
  - 26.5.4 DMA
    388
  - 26.5.5 Interrupts
    388
  - 26.5.6 Events
    388
  - 26.5.7 Debug Operation
    389
  - 26.5.8 Register Access Protection
    389
  - 26.5.9 Analog Connections
    389
- 26.6 Functional Description
  389
  - 26.6.1 Principle of Operation
    389
  - 26.6.2 Basic Operation
    390
  - 26.6.3 Additional Features
    398
    - 26.6.3.1 SMBus
      398
    - 26.6.3.2 Smart Mode
      398
    - 26.6.3.3 4-Wire Mode
      398
    - 26.6.3.4 Quick Command
      399
  - 26.6.4 Interrupts
    399
  - 26.6.5 Sleep Mode Operation
    399
  - 26.6.6 Synchronization
    400
- 26.7 Register Summary
  401
- 26.8 Register Description
  405
  - 26.8.1 I2C Slave Register Description
    406
    - 26.8.1.1 Control A
      406
    - 26.8.1.2 Control B
      409
    - 26.8.1.3 Interrupt Enable Clear
      412
    - 26.8.1.4 Interrupt Enable Set
      413
    - 26.8.1.5 Interrupt Flag Status and Clear
      414
    - 26.8.1.6 Status
      415
    - 26.8.1.7 Address
      417
    - 26.8.1.8 Data
      419
  - 26.8.2 I2C Master Register Description
    420
    - 26.8.2.1 Control A
      420
    - 26.8.2.2 Control B
      423
    - 26.8.2.3 Debug Control
      425
    - 26.8.2.4 Baud Rate
      426
    - 26.8.2.5 Interrupt Enable Clear
      427
    - 26.8.2.6 Interrupt Enable Set
      428
    - 26.8.2.7 Interrupt Flag Status and Clear
      429
    - 26.8.2.8 Status
      430
    - 26.8.2.9 Address
      432
    - 26.8.2.10 Data
      433
27. TC – Timer/Counter
434
- 27.1 Overview
  434
- 27.2 Features
  434
- 27.3 Block Diagram
  435
- 27.4 Signal Description
  436
- 27.5 Product Dependencies
  436
  - 27.5.1 I/O Lines
    436
  - 27.5.2 Power Management
    436
  - 27.5.3 Clocks
    436
  - 27.5.4 Interrupts
    436
  - 27.5.5 Events
    436
  - 27.5.6 Debug Operation
    436
  - 27.5.7 Register Access Protection
    436
  - 27.5.8 Analog Connections
    437
- 27.6 Functional Description
  437
  - 27.6.1 Principle of Operation
    437
  - 27.6.2 Basic Operation
    437
    - 27.6.2.1 Initialization
      437
    - 27.6.2.2 Enabling, Disabling and Resetting
      438
    - 27.6.2.3 Prescaler Selection
      438
    - 27.6.2.4 TC Mode
      438
    - 27.6.2.5 Counter Operations
      439
    - 27.6.2.6 Compare Operations
      440
    - 27.6.2.7 Capture Operations
      443
  - 27.6.3 Additional Features
    444
    - 27.6.3.1 One-Shot Operation
      444
  - 27.6.4 Interrupts
    444
  - 27.6.5 Events
    445
  - 27.6.6 Sleep Mode Operation
    445
  - 27.6.7 Synchronization
    445
- 27.7 Register Summary
  447
- 27.8 Register Description
  450
  - 27.8.1 Control A
    451
  - 27.8.2 Read Request
    454
  - 27.8.3 Control B Clear
    455
  - 27.8.4 Control B Set
    457
  - 27.8.5 Control C
    459
  - 27.8.6 Debug Control
    460
  - 27.8.7 Event Control
    461
  - 27.8.8 Interrupt Enable Clear
    463
  - 27.8.9 Interrupt Enable Set
    464
  - 27.8.10 Interrupt Flag Status and Clear
    465
  - 27.8.11 Status
    466
  - 27.8.12 Counter Value
    467
    - 27.8.12.1 8-Bit Mode
      467
    - 27.8.12.2 16-Bit Mode
      468
    - 27.8.12.3 32-Bit Mode
      469
  - 27.8.13 Period Value
    470
    - 27.8.13.1 8-Bit Mode
      470
  - 27.8.14 Compare/Capture
    471
    - 27.8.14.1 8-Bit Mode
      471
    - 27.8.14.2 16-Bit Mode
      472
    - 27.8.14.3 32-Bit Mode
      473
28. ADC – Analog-to-Digital Converter
474
- 28.1 Overview
  474
- 28.2 Features
  474
- 28.3 Block Diagram
  475
- 28.4 Signal Description
  475
- 28.5 Product Dependencies
  476
  - 28.5.1 I/O Lines
    476
  - 28.5.2 Power Management
    476
  - 28.5.3 Clocks
    476
  - 28.5.4 DMA
    476
  - 28.5.5 Interrupts
    476
  - 28.5.6 Events
    476
  - 28.5.7 Debug Operation
    476
  - 28.5.8 Register Access Protection
    476
  - 28.5.9 Analog Connections
    476
  - 28.5.10 Calibration
    477
- 28.6 Functional Description
  477
  - 28.6.1 Principle of Operation
    477
  - 28.6.2 Basic Operation
    477
  - 28.6.3 Prescaler
    478
  - 28.6.4 ADC Resolution
    478
  - 28.6.5 Differential and Single-Ended Conversions
    479
    - 28.6.5.1 Conversion Timing
      479
  - 28.6.6 Accumulation
    481
  - 28.6.7 Averaging
    481
  - 28.6.8 Oversampling and Decimation
    482
  - 28.6.9 Window Monitor
    482
  - 28.6.10 Offset and Gain Correction
    483
  - 28.6.11 Interrupts
    483
  - 28.6.12 Events
    484
  - 28.6.13 Sleep Mode Operation
    484
  - 28.6.14 Synchronization
    484
- 28.7 Register Summary
  486
- 28.8 Register Description
  488
  - 28.8.1 Control A
    488
  - 28.8.2 Reference Control
    490
  - 28.8.3 Average Control
    491
  - 28.8.4 Sampling Time Control
    492
  - 28.8.5 Control B
    493
  - 28.8.6 Window Monitor Control
    495
  - 28.8.7 Software Trigger
    496
  - 28.8.8 Input Control
    497
  - 28.8.9 Event Control
    501
  - 28.8.10 Interrupt Enable Clear
    502
  - 28.8.11 Interrupt Enable Set
    503
  - 28.8.12 Interrupt Flag Status and Clear
    504
  - 28.8.13 Status
    505
  - 28.8.14 Result
    506
  - 28.8.15 Window Monitor Lower Threshold
    507
  - 28.8.16 Window Monitor Upper Threshold
    508
  - 28.8.17 Gain Correction
    509
  - 28.8.18 Offset Correction
    510
  - 28.8.19 Calibration
    511
  - 28.8.20 Debug Control
    512
29. AC – Analog Comparators
513
- 29.1 Overview
  513
- 29.2 Features
  513
- 29.3 Block Diagram
  514
- 29.4 Signal Description
  514
- 29.5 Product Dependencies
  514
  - 29.5.1 I/O Lines
    514
  - 29.5.2 Power Management
    515
  - 29.5.3 Clocks
    515
  - 29.5.4 Interrupts
    515
  - 29.5.5 Events
    515
  - 29.5.6 Debug Operation
    515
  - 29.5.7 Register Access Protection
    515
  - 29.5.8 Analog Connections
    515
  - 29.5.9 Other Dependencies
    515
- 29.6 Functional Description
  516
  - 29.6.1 Principle of Operation
    516
  - 29.6.2 Basic Operation
    516
  - 29.6.3 Selecting Comparator Inputs
    518
  - 29.6.4 Window Operation
    518
  - 29.6.5 Voltage Doubler
    519
  - 29.6.6 VDDANA Scaler
    519
  - 29.6.7 Input Hysteresis
    520
  - 29.6.8 Propagation Delay vs. Power Consumption
    520
  - 29.6.9 Filtering
    520
  - 29.6.10 Comparator Output
    521
  - 29.6.11 Offset Compensation
    521
- 29.7 Additional Features
  522
- 29.8 Register Summary
  525
- 29.9 Register Description
  526
  - 29.9.1 Control A
    526
  - 29.9.2 Control B
    528
  - 29.9.3 Event Control
    529
  - 29.9.4 Interrupt Enable Clear
    530
  - 29.9.5 Interrupt Enable Set
    531
  - 29.9.6 Interrupt Flag Status and Clear
    532
  - 29.9.7 Status A
    533
  - 29.9.8 Status B
    534
  - 29.9.9 Status C
    535
  - 29.9.10 Window Control
    536
  - 29.9.11 Scaler n
    537
  - 29.9.12 Comparator Control n
    538
30. DAC – Digital-to-Analog Converter
542
- 30.1 Overview
  542
- 30.2 Features
  542
- 30.3 Block Diagram
  542
- 30.4 Signal Description
  542
- 30.5 Product Dependencies
  543
  - 30.5.1 I/O Lines
    543
  - 30.5.2 Power Management
    543
  - 30.5.3 Clocks
    543
  - 30.5.4 DMA
    543
  - 30.5.5 Interrupts
    543
  - 30.5.6 Events
    543
  - 30.5.7 Debug Operation
    543
  - 30.5.8 Register Access Protection
    543
  - 30.5.9 Analog Connections
    543
- 30.6 Functional Description
  544
  - 30.6.1 Principle of Operation
    544
  - 30.6.2 Basic Operation
    544
  - 30.6.3 Additional Features
    544
    - 30.6.3.1 Conversion Range
      544
    - 30.6.3.2 DAC as an Internal Reference
      544
    - 30.6.3.3 Data Buffer
      544
    - 30.6.3.4 Voltage Pump
      545
    - 30.6.3.5 Sampling Period
      545
  - 30.6.4 DMA Operation
    545
  - 30.6.5 Interrupts
    545
  - 30.6.6 Events
    545
  - 30.6.7 Sleep Mode Operation
    546
  - 30.6.8 Synchronization
    546
- 30.7 Register Summary
  547
- 30.8 Register Description
  548
  - 30.8.1 Control A
    549
  - 30.8.2 Control B
    550
  - 30.8.3 Event Control
    551
  - 30.8.4 Interrupt Enable Clear
    552
  - 30.8.5 Interrupt Enable Set
    553
  - 30.8.6 Interrupt Flag Status and Clear
    554
  - 30.8.7 Status
    555
  - 30.8.8 Data
    556
  - 30.8.9 Data Buffer
    557
31. PTC - Peripheral Touch Controller
558
- 31.1 Overview
  558
- 31.2 Features
  558
- 31.3 Block Diagram
  559
- 31.4 Signal Description
  560
- 31.5 Product Dependencies
  560
  - 31.5.1 I/O Lines
    560
  - 31.5.2 Clocks
    561
- 31.6 Functional Description
  562
32. Electrical Characteristics
563
- 32.1 Disclaimer
  563
- 32.2 Absolute Maximum Ratings
  563
- 32.3 General Operating Ratings
  564
- 32.4 Supply Characteristics
  565
- 32.5 Maximum Clock Frequencies
  565
- 32.6 Power Consumption
  567
- 32.7 I/O Pin Characteristics
  570
  - 32.7.1 Normal I/O Pins
    570
  - 32.7.2 I2C Pins
    572
  - 32.7.3 XOSC Pin
    572
  - 32.7.4 XOSC32 Pin
    572
  - 32.7.5 External Reset Pin
    572
- 32.8 Analog Characteristics
  573
- 32.9 NVM Characteristics
  585
- 32.10 Oscillators Characteristics
  586
- 32.11 PTC Typical Characteristics
  591
- 32.12 Timing Characteristics
  595
  - 32.12.1 External Reset
    595
  - 32.12.2 SERCOM in SPI Mode Timing
    595
  - 32.12.3 SERCOM in I2C Mode Timing
    598
  - 32.12.4 SWD Timing
    599
33. Packaging Information
600
- 33.1 Thermal Considerations
  600
  - 33.1.1 Thermal Resistance Data
    600
  - 33.1.2 Junction Temperature
    600
- 33.2 Package Drawings
  601
  - 33.2.1 64-pin TQFP
    601
  - 33.2.2 64-pin QFN
    602
  - 33.2.3 48-pin TQFP
    603
  - 33.2.4 48-pin QFN
    604
  - 33.2.5 32-pin TQFP
    605
  - 33.2.6 32-pin QFN
    606
- 33.3 Soldering Profile
  607
34. Schematic Checklist
608
- 34.1 Introduction
  608
- 34.2 Power Supply
  608
  - 34.2.1 Power Supply Connections
    608
- 34.3 External Analog Reference Connections
  609
- 34.4 External Reset Circuit
  611
- 34.5 Unused or Unconnected Pins
  611
- 34.6 Clocks and Crystal Oscillators
  612
- 34.7 Programming and Debug Ports
  615
35. Errata
619
- 35.1 Revision D
  619
  - 35.1.1 NVMCTRL
    619
  - 35.1.2 Device
    619
  - 35.1.3 PM
    620
  - 35.1.4 XOSC32K
    620
  - 35.1.5 DFLL48M
    620
- 35.2 Revision C
  621
  - 35.2.1 NVMCTRL
    621
  - 35.2.2 VREG
    621
  - 35.2.3 Device
    621
  - 35.2.4 PM
    623
  - 35.2.5 GCLK
    623
  - 35.2.6 XOSC32K
    624
  - 35.2.7 DFLL48M
    624
  - 35.2.8 EVSYS
    625
  - 35.2.9 SERCOM
    625
  - 35.2.10 ADC
    626
  - 35.2.11 Flash
    626
- 35.3 Revision B
  627
  - 35.3.1 NVMCTRL
    627
  - 35.3.2 VREG
    627
  - 35.3.3 Device
    627
  - 35.3.4 PM
    629
  - 35.3.5 GCLK
    629
  - 35.3.6 XOSC32K
    630
  - 35.3.7 DFLL48M
    630
  - 35.3.8 EVSYS
    631
  - 35.3.9 SERCOM
    631
  - 35.3.10 ADC
    632
  - 35.3.11 PTC
    632
  - 35.3.12 Flash
    632
- 35.4 Revision A
  633
36. Datasheet Revision History
634
- 36.1 Rev. K – 05/2014
  634
- 36.2 Rev. J – 12/2013
  636
- 36.3 Rev. I – 12/2013
  636
- 36.4 Rev. H – 10/2013
  643
- 36.5 Rev. G – 10/2013
  644
- 36.6 Rev. F – 10/2013
  645
- 36.7 Rev. E – 09/2013
  645
- 36.8 Rev. D – 08/2013
  645
- 36.9 Rev. C – 07/2013
  646
- 36.10 Rev. B – 07/2013
  647
- 36.11 Rev. A – 06/2013
  648
Appendix A. Conventions
649
- A.1 Numerical Notation
  649
- A.2 Memory Size and Type
  649
- A.3 Frequency and Time
  649
- A.4 Registers and Bits
  650
Appendix B. Acronyms and Abbreviations
651
Table of Contents
654

Scheda Tecnica (ATSAMD20-XPRO)

Dimensioni:

8,46 MB
Pagine:

660
Language:

English

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