Manuali utente per IBM PPC440X5

Sommario

• Contents

  3
• Figures

  15
• Tables

  19
• About This Book

  23
  • Who Should Use This Book

    23
  • How to Use This Book

    23
  • Notation

    24
  • Related Publications

    25
• 1. Overview

  27
  • 1.1 PPC440x5 Features

    27
  • 1.2 The PPC440x5 as a PowerPC Implementation

    29
  • 1.3 PPC440x5 Organization

    30
    • 1.3.1 Superscalar Instruction Unit

      30
    • 1.3.2 Execution Pipelines

      31
    • 1.3.3 Instruction and Data Cache Controllers

      31
      • 1.3.3.1 Instruction Cache Controller (ICC)

        31
      • 1.3.3.2 Data Cache Controller (DCC)

        32
    • 1.3.4 Memory Management Unit (MMU)

      32
    • 1.3.5 Timers

      34
    • 1.3.6 Debug Facilities

      34
      • 1.3.6.1 Debug Modes

        34
      • 1.3.6.2 Development Tool Support

        35
  • 1.4 Core Interfaces

    35
    • 1.4.1 Processor Local Bus (PLB)

      36
    • 1.4.2 Device Control Register (DCR) Interface

      36
    • 1.4.3 Auxiliary Processor Unit (APU) Port

      36
    • 1.4.4 JTAG Port

      37
• 2. Programming Model

  39
  • 2.1 Storage Addressing

    39
    • 2.1.1 Storage Operands

      39
    • 2.1.2 Effective Address Calculation

      41
      • 2.1.2.1 Data Storage Addressing Modes

        41
      • 2.1.2.2 Instruction Storage Addressing Modes

        41
    • 2.1.3 Byte Ordering

      42
      • 2.1.3.1 Structure Mapping Examples

        43
      • 2.1.3.2 Instruction Byte Ordering

        44
      • 2.1.3.3 Data Byte Ordering

        45
      • 2.1.3.4 Byte-Reverse Instructions

        46
  • 2.2 Registers

    47
    • 2.2.1 Register Types

      52
      • 2.2.1.1 General Purpose Registers

        52
      • 2.2.1.2 Special Purpose Registers

        52
      • 2.2.1.3 Condition Register

        52
      • 2.2.1.4 Machine State Register

        53
      • 2.2.1.5 Device Control Registers

        53
  • 2.3 Instruction Classes

    53
    • 2.3.1 Defined Instruction Class

      53
    • 2.3.2 Allocated Instruction Class

      54
    • 2.3.3 Preserved Instruction Class

      55
    • 2.3.4 Reserved Instruction Class

      56
  • 2.4 Implemented Instruction Set Summary

    56
    • 2.4.1 Integer Instructions

      57
      • 2.4.1.1 Integer Storage Access Instructions

        57
      • 2.4.1.2 Integer Arithmetic Instructions

        58
      • 2.4.1.3 Integer Logical Instructions

        59
      • 2.4.1.4 Integer Compare Instructions

        59
      • 2.4.1.5 Integer Trap Instructions

        59
      • 2.4.1.6 Integer Rotate Instructions

        59
      • 2.4.1.7 Integer Shift Instructions

        60
      • 2.4.1.8 Integer Select Instruction

        60
    • 2.4.2 Branch Instructions

      60
    • 2.4.3 Processor Control Instructions

      60
      • 2.4.3.1 Condition Register Logical Instructions

        61
      • 2.4.3.2 Register Management Instructions

        61
      • 2.4.3.3 System Linkage Instructions

        61
      • 2.4.3.4 Processor Synchronization Instruction

        61
    • 2.4.4 Storage Control Instructions

      62
      • 2.4.4.1 Cache Management Instructions

        62
      • 2.4.4.2 TLB Management Instructions

        62
      • 2.4.4.3 Storage Synchronization Instructions

        63
    • 2.4.5 Allocated Instructions

      63
  • 2.5 Branch Processing

    64
    • 2.5.1 Branch Addressing

      64
    • 2.5.2 Branch Instruction BI Field

      64
    • 2.5.3 Branch Instruction BO Field

      64
    • 2.5.4 Branch Prediction

      65
    • 2.5.5 Branch Control Registers

      66
      • 2.5.5.1 Link Register (LR)

        66
      • 2.5.5.2 Count Register (CTR)

        67
      • 2.5.5.3 Condition Register (CR)

        67
  • 2.6 Integer Processing

    71
    • 2.6.1 General Purpose Registers (GPRs)

      71
    • 2.6.2 Integer Exception Register (XER)

      72
      • 2.6.2.1 Summary Overflow (SO) Field

        73
      • 2.6.2.2 Overflow (OV) Field

        74
      • 2.6.2.3 Carry (CA) Field

        74
  • 2.7 Processor Control

    74
    • 2.7.1 Special Purpose Registers General (USPRG0, SPRG0–SPRG7)

      75
    • 2.7.2 Processor Version Register (PVR)

      75
    • 2.7.3 Processor Identification Register (PIR)

      76
    • 2.7.4 Core Configuration Register 0 (CCR0)

      76
    • 2.7.5 Core Configuration Register 1 (CCR1)

      78
    • 2.7.6 Reset Configuration (RSTCFG)

      79
  • 2.8 User and Supervisor Modes

    80
    • 2.8.1 Privileged Instructions

      80
    • 2.8.2 Privileged SPRs

      81
  • 2.9 Speculative Accesses

    81
  • 2.10 Synchronization

    82
    • 2.10.1 Context Synchronization

      82
    • 2.10.2 Execution Synchronization

      83
    • 2.10.3 Storage Ordering and Synchronization

      84
• 3. Initialization

  85
  • 3.1 PPC440x5 Core State After Reset

    85
  • 3.2 Reset Types

    89
  • 3.3 Reset Sources

    89
  • 3.4 Initialization Software Requirements

    89
• 4. Instruction and Data Caches

  95
  • 4.1 Cache Array Organization and Operation

    95
    • 4.1.1 Cache Line Replacement Policy

      96
    • 4.1.2 Cache Locking and Transient Mechanism

      99
  • 4.2 Instruction Cache Controller

    103
    • 4.2.1 ICC Operations

      104
    • 4.2.2 Speculative Prefetch Mechanism

      105
    • 4.2.3 Instruction Cache Coherency

      106
      • 4.2.3.1 Self-Modifying Code

        106
      • 4.2.3.2 Instruction Cache Synonyms

        107
    • 4.2.4 Instruction Cache Control and Debug

      108
      • 4.2.4.1 Instruction Cache Management and Debug Instruction Summary

        108
      • 4.2.4.2 Core Configuration Register 0 (CCR0)

        108
      • 4.2.4.3 Core Configuration Register 1 (CCR1)

        110
      • 4.2.4.4 icbt Operation

        111
      • 4.2.4.5 icread Operation

        112
      • 4.2.4.6 Instruction Cache Parity Operations

        114
      • 4.2.4.7 Simulating Instruction Cache Parity Errors for Software Testing

        114
  • 4.3 Data Cache Controller

    115
    • 4.3.1 DCC Operations

      116
      • 4.3.1.1 Load and Store Alignment

        117
      • 4.3.1.2 Load Operations

        118
      • 4.3.1.3 Store Operations

        119
      • 4.3.1.4 Line Flush Operations

        121
      • 4.3.1.5 Data Read PLB Interface Requests

        122
      • 4.3.1.6 Data Write PLB Interface Requests

        123
      • 4.3.1.7 Storage Access Ordering

        124
    • 4.3.2 Data Cache Coherency

      124
    • 4.3.3 Data Cache Control and Debug

      125
      • 4.3.3.1 Data Cache Management and Debug Instruction Summary

        125
      • 4.3.3.2 Core Configuration Register 0 (CCR0)

        126
      • 4.3.3.3 Core Configuration Register 1 (CCR1)

        126
      • 4.3.3.4 dcbt and dcbtst Operation

        126
      • 4.3.3.5 dcread Operation

        127
      • 4.3.3.6 Data Cache Parity Operations

        129
      • 4.3.3.7 Simulating Data Cache Parity Errors for Software Testing

        130
• 5. Memory Management

  133
  • 5.1 MMU Overview

    133
    • 5.1.1 Support for PowerPC Book-E MMU Architecture

      133
  • 5.2 Translation Lookaside Buffer

    134
  • 5.3 Page Identification

    138
    • 5.3.1 Virtual Address Formation

      138
    • 5.3.2 Address Space Identifier Convention

      138
    • 5.3.3 TLB Match Process

      139
  • 5.4 Address Translation

    140
  • 5.5 Access Control

    142
    • 5.5.1 Execute Access

      142
    • 5.5.2 Write Access

      142
    • 5.5.3 Read Access

      143
    • 5.5.4 Access Control Applied to Cache Management Instructions

      143
  • 5.6 Storage Attributes

    145
    • 5.6.1 Write-Through (W)

      145
    • 5.6.2 Caching Inhibited (I)

      145
    • 5.6.3 Memory Coherence Required (M)

      146
    • 5.6.4 Guarded (G)

      146
    • 5.6.5 Endian (E)

      146
    • 5.6.6 User-Definable (U0–U3)

      147
    • 5.6.7 Supported Storage Attribute Combinations

      147
  • 5.7 Storage Control Registers

    147
    • 5.7.1 Memory Management Unit Control Register (MMUCR)

      148
    • 5.7.2 Process ID (PID)

      151
  • 5.8 Shadow TLB Arrays

    151
  • 5.9 TLB Management Instructions

    152
    • 5.9.1 TLB Search Instruction (tlbsx[.])

      153
    • 5.9.2 TLB Read/Write Instructions (tlbre/tlbwe)

      153
    • 5.9.3 TLB Sync Instruction (tlbsync)

      154
  • 5.10 Page Reference and Change Status Management

    154
  • 5.11 TLB Parity Operations

    155
    • 5.11.1 Reading TLB Parity Bits with tlbre

      155
    • 5.11.2 Simulating TLB Parity Errors for Software Testing

      156
• 6. Interrupts and Exceptions

  159
  • 6.1 Overview

    159
  • 6.2 Interrupt Classes

    159
    • 6.2.1 Asynchronous Interrupts

      159
    • 6.2.2 Synchronous Interrupts

      159
      • 6.2.2.1 Synchronous, Precise Interrupts

        160
      • 6.2.2.2 Synchronous, Imprecise Interrupts

        160
    • 6.2.3 Critical and Non-Critical Interrupts

      161
    • 6.2.4 Machine Check Interrupts

      161
  • 6.3 Interrupt Processing

    162
    • 6.3.1 Partially Executed Instructions

      164
  • 6.4 Interrupt Processing Registers

    165
    • 6.4.1 Machine State Register (MSR)

      165
    • 6.4.2 Save/Restore Register0(SRR0)

      167
    • 6.4.3 Save/Restore Register1(SRR1)

      167
    • 6.4.4 Critical Save/Restore Register 0 (CSRR0)

      168
    • 6.4.5 Critical Save/Restore Register 1 (CSRR1)

      168
    • 6.4.6 Machine Check Save/Restore Register 0 (MCSRR0)

      169
    • 6.4.7 Machine Check Save/Restore Register 1 (MCSRR1)

      169
    • 6.4.8 Data Exception Address Register (DEAR)

      170
    • 6.4.9 Interrupt Vector Offset Registers (IVOR0–IVOR15)

      170
    • 6.4.10 Interrupt Vector Prefix Register (IVPR)

      171
    • 6.4.11 Exception Syndrome Register (ESR)

      172
    • 6.4.12 Machine Check Status Register (MCSR)

      174
  • 6.5 Interrupt Definitions

    175
    • 6.5.1 Critical Input Interrupt

      178
    • 6.5.2 Machine Check Interrupt

      178
    • 6.5.3 Data Storage Interrupt

      181
    • 6.5.4 Instruction Storage Interrupt

      184
    • 6.5.5 External Input Interrupt

      185
    • 6.5.6 Alignment Interrupt

      185
    • 6.5.7 Program Interrupt

      187
    • 6.5.8 Floating-Point Unavailable Interrupt

      190
    • 6.5.9 System Call Interrupt

      190
    • 6.5.10 Auxiliary Processor Unavailable Interrupt

      191
    • 6.5.11 Decrementer Interrupt

      191
    • 6.5.12 Fixed-Interval Timer Interrupt

      192
    • 6.5.13 Watchdog Timer Interrupt

      192
    • 6.5.14 Data TLB Error Interrupt

      193
    • 6.5.15 Instruction TLB Error Interrupt

      194
    • 6.5.16 Debug Interrupt

      195
  • 6.6 Interrupt Ordering and Masking

    199
    • 6.6.1 Interrupt Ordering Software Requirements

      199
    • 6.6.2 Interrupt Order

      201
  • 6.7 Exception Priorities

    202
    • 6.7.1 Exception Priorities for Integer Load, Store, and Cache Management Instructions

      202
    • 6.7.2 Exception Priorities for Floating-Point Load and Store Instructions

      203
    • 6.7.3 Exception Priorities for Allocated Load and Store Instructions

      203
    • 6.7.4 Exception Priorities for Floating-Point Instructions (Other)

      204
    • 6.7.5 Exception Priorities for Allocated Instructions (Other)

      205
    • 6.7.6 Exception Priorities for Privileged Instructions

      205
    • 6.7.7 Exception Priorities for Trap Instructions

      206
    • 6.7.8 Exception Priorities for System Call Instruction

      206
    • 6.7.9 Exception Priorities for Branch Instructions

      207
    • 6.7.10 Exception Priorities for Return From Interrupt Instructions

      207
    • 6.7.11 Exception Priorities for Preserved Instructions

      207
    • 6.7.12 Exception Priorities for Reserved Instructions

      207
    • 6.7.13 Exception Priorities for All Other Instructions

      208
• 7. Timer Facilities

  209
  • 7.1 Time Base

    209
    • 7.1.1 Reading the Time Base

      210
    • 7.1.2 Writing the Time Base

      210
  • 7.2 Decrementer (DEC)

    211
  • 7.3 Fixed Interval Timer (FIT)

    212
  • 7.4 Watchdog Timer

    213
  • 7.5 Timer Control Register (TCR)

    215
  • 7.6 Timer Status Register (TSR)

    216
  • 7.7 Freezing the Timer Facilities

    217
  • 7.8 Selection of the Timer Clock Source

    217
• 8. Debug Facilities

  219
  • 8.1 Support for Development Tools

    219
  • 8.2 Debug Modes

    219
    • 8.2.1 Internal Debug Mode

      219
    • 8.2.2 External Debug Mode

      220
    • 8.2.3 Debug Wait Mode

      220
    • 8.2.4 Trace Debug Mode

      221
  • 8.3 Debug Events

    221
    • 8.3.1 Instruction Address Compare (IAC) Debug Event

      222
      • 8.3.1.1 IAC Debug Event Fields

        222
      • 8.3.1.2 IAC Debug Event Processing

        225
    • 8.3.2 Data Address Compare (DAC) Debug Event

      226
      • 8.3.2.1 DAC Debug Event Fields

        226
      • 8.3.2.2 DAC Debug Event Processing

        229
      • 8.3.2.3 DAC Debug Events Applied to Instructions that Result in Multiple Storage Accesses

        230
      • 8.3.2.4 DAC Debug Events Applied to Various Instruction Types

        230
    • 8.3.3 Data Value Compare (DVC) Debug Event

      231
      • 8.3.3.1 DVC Debug Event Fields

        232
      • 8.3.3.2 DVC Debug Event Processing

        233
      • 8.3.3.3 DVC Debug Events Applied to Instructions that Result in Multiple Storage Accesses

        233
      • 8.3.3.4 DVC Debug Events Applied to Various Instruction Types

        233
    • 8.3.4 Branch Taken (BRT) Debug Event

      234
    • 8.3.5 Trap (TRAP) Debug Event

      234
    • 8.3.6 Return (RET) Debug Event

      235
    • 8.3.7 Instruction Complete (ICMP) Debug Event

      235
    • 8.3.8 Interrupt (IRPT) Debug Event

      236
    • 8.3.9 Unconditional Debug Event (UDE)

      237
    • 8.3.10 Debug Event Summary

      237
  • 8.4 Debug Reset

    238
  • 8.5 Debug Timer Freeze

    238
  • 8.6 Debug Registers

    238
    • 8.6.1 Debug Control Register 0 (DBCR0)

      239
    • 8.6.2 Debug Control Register 1 (DBCR1)

      240
    • 8.6.3 Debug Control Register 2 (DBCR2)

      243
    • 8.6.4 Debug Status Register (DBSR)

      244
    • 8.6.5 Instruction Address Compare Registers (IAC1–IAC4)

      245
    • 8.6.6 Data Address Compare Registers (DAC1–DAC2)

      246
    • 8.6.7 Data Value Compare Registers (DVC1–DVC2)

      246
    • 8.6.8 Debug Data Register (DBDR)

      247
• 9. Instruction Set

  249
  • 9.1 Instruction Set Portability

    250
  • 9.2 Instruction Formats

    250
  • 9.3 Pseudocode

    251
    • 9.3.1 Operator Precedence

      253
  • 9.4 Register Usage

    253
  • 9.5 Alphabetical Instruction Listing

    254
    • add

      255
    • addc

      256
    • adde

      257
    • addi

      258
    • addic

      259
    • addic.

      260
    • addis

      261
    • addme

      262
    • addze

      263
    • and

      264
    • andc

      265
    • andi.

      266
    • andis.

      267
    • b

      268
    • bc

      269
    • bcctr

      275
    • bclr

      278
    • cmp

      282
    • cmpi

      283
    • cmpl

      284
    • cmpli

      285
    • cntlzw

      286
    • crand

      287
    • crandc

      288
    • creqv

      289
    • crnand

      290
    • crnor

      291
    • cror

      292
    • crorc

      293
    • crxor

      294
    • dcba

      295
    • dcbf

      296
    • dcbi

      297
    • dcbst

      298
    • dcbt

      299
    • dcbtst

      300
    • dcbz

      302
    • dccci

      304
    • dcread

      305
    • divw

      307
    • divwu

      308
    • dlmzb

      309
    • eqv

      310
    • extsb

      311
    • extsh

      312
    • icbi

      313
    • icbt

      314
    • iccci

      316
    • icread

      317
    • isel

      319
    • isync

      320
    • lbz

      321
    • lbzu

      322
    • lbzux

      323
    • lbzx

      324
    • lha

      325
    • lhau

      326
    • lhaux

      327
    • lhax

      328
    • lhbrx

      329
    • lhz

      330
    • lhzu

      331
    • lhzux

      332
    • lhzx

      333
    • lmw

      334
    • lswi

      335
    • lswx

      337
    • lwarx

      339
    • lwbrx

      340
    • lwz

      341
    • lwzu

      342
    • lwzux

      343
    • lwzx

      344
    • macchw

      345
    • macchws

      346
    • macchwsu

      347
    • macchwu

      348
    • machhw

      349
    • machhws

      350
    • machhwsu

      351
    • machhwu

      352
    • maclhw

      353
    • maclhws

      354
    • maclhwsu

      355
    • maclhwu

      356
    • mbar

      357
    • mcrf

      358
    • mcrxr

      359
    • mfcr

      360
    • mfdcr

      361
    • mfmsr

      362
    • mfspr

      363
    • msync

      366
    • mtcrf

      367
    • mtdcr

      368
    • mtmsr

      369
    • mtspr

      370
    • mulchw

      373
    • mulchwu

      374
    • mulhhw

      375
    • mulhhwu

      376
    • mulhw

      377
    • mulhwu

      378
    • mullhw

      379
    • mullhwu

      380
    • mulli

      381
    • mullw

      382
    • nand

      383
    • neg

      384
    • nmacchw

      385
    • nmacchws

      386
    • nmachhw

      387
    • nmachhws

      388
    • nmaclhw

      389
    • nmaclhws

      390
    • nor

      391
    • or

      392
    • orc

      393
    • ori

      394
    • oris

      395
    • rfci

      396
    • rfi

      397
    • rfmci

      398
    • rlwimi

      399
    • rlwinm

      400
    • rlwnm

      403
    • sc

      404
    • slw

      405
    • sraw

      406
    • srawi

      407
    • srw

      408
    • stb

      409
    • stbu

      410
    • stbux

      411
    • stbx

      412
    • sth

      413
    • sthbrx

      414
    • sthu

      415
    • sthux

      416
    • sthx

      417
    • stmw

      418
    • stswi

      419
    • stswx

      421
    • stw

      422
    • stwbrx

      423
    • stwcx.

      424
    • stwu

      426
    • stwux

      427
    • stwx

      428
    • subf

      429
    • subfc

      430
    • subfe

      431
    • subfic

      432
    • subfme

      433
    • subfze

      434
    • tlbre

      435
    • tlbsx

      437
    • tlbsync

      438
    • tlbwe

      439
    • tw

      440
    • twi

      443
    • wrtee

      446
    • wrteei

      447
    • xor

      448
    • xori

      449
    • xoris

      450
• 10. Register Summary

  451
  • 10.1 Register Categories

    451
  • 10.2 Reserved Fields

    457
  • 10.3 Device Control Registers

    457
  • 10.4 Alphabetical Register Listing

    459
    • CCR0

      460
    • CCR1

      462
    • CR

      464
    • CSRR0

      465
    • CSRR1

      466
    • CTR

      467
    • DAC1–DAC2

      468
    • DBCR0

      469
    • DBCR1

      471
    • DBCR2

      473
    • DBDR

      475
    • DBSR

      476
    • DCDBTRH

      478
    • DCDBTRL

      479
    • DEAR

      480
    • DEC

      481
    • DECAR

      482
    • DNV0–DNV3

      483
    • DTV0–DTV3

      484
    • DVC1–DVC2

      485
    • DVLIM

      486
    • ESR

      487
    • GPR0–GPR31

      489
    • IAC1–IAC4

      490
    • ICDBDR

      491
    • ICDBTRH

      492
    • ICDBTRL

      493
    • INV0–INV3

      494
    • ITV0–ITV3

      495
    • IVLIM

      496
    • IVOR0–IVOR15

      497
    • IVPR

      498
    • LR

      499
    • MCSR

      500
    • MCSRR0

      501
    • MCSRR1

      502
    • MMUCR

      503
    • MSR

      504
    • PID

      506
    • PIR

      507
    • PVR

      508
    • RSTCFG

      509
    • SPRG0–SPRG7

      510
    • SRR0

      511
    • SRR1

      512
    • TBL

      513
    • TBU

      514
    • TCR

      515
    • TSR

      516
    • USPRG0

      517
    • XER

      518
• Appendix A. Instruction Summary

  519
  • A.1 Instruction Formats

    519
    • A.1.1 Instruction Fields

      520
    • A.1.2 Instruction Format Diagrams

      521
      • A.1.2.1 I-Form

        522
      • A.1.2.2 B-Form

        522
      • A.1.2.3 SC-Form

        522
      • A.1.2.4 D-Form

        522
      • A.1.2.5 X-Form

        523
      • A.1.2.6 XL-Form

        524
      • A.1.2.7 XFX-Form

        524
      • A.1.2.8 XO-Form

        524
      • A.1.2.9 M-Form

        524
  • A.2 Alphabetical Summary of Implemented Instructions

    524
  • A.3 Allocated Instruction Opcodes

    557
  • A.4 Preserved Instruction Opcodes

    557
  • A.5 Reserved Instruction Opcodes

    558
  • A.6 Implemented Instructions Sorted by Opcode

    559
• Appendix B. PPC440x5 Core Compiler Optimizations

  569
• Index

  571
• Revision Log

  589