Manuale UtenteSommarioContents3Figures11Tables12Revision History13Introduction15Terminology15Reference Documents16Intel® 815 Chipset Overview17I/O Controller Hub18Intel® 82815 Chipset GMCH Overview18Host Interface19System Memory Interface20Multiplexed AGP and Display Cache Interface20Hub Interface21Intel® 82815 Chipset GMCH Integrated Graphics Support21System Clocking22GMCH Power Delivery22Three PCI Devices on GMCH22Multi-Mode Capability Requirements23Supported Single Monitor and Multi-monitor Configurations23System Startup25Software Start-Up Sequence26Graphics Driver Startup27Switching Device modes28System Address Map29Memory and I/O Space Registers30GC Register Memory Address Map32VGA and Extended VGA Register Map36VGA and Extended VGA I/O and Memory Register Map37Indirect VGA and Extended VGA Register Indices38Graphics Address Translation41Memory Buffers for GC’s Instruction Interface42Graphics Translation Table (GTT) Range Definition43Basic Initialization Procedures45Initialization Sequence45Hardware Detection (Probe)45Frame Buffer Initialization46Hardware Register Initialization47Color vs. Monochrome Monitors47Protect Registers: Locking and Unlocking47Checking Memory Frequency47Hardware State47Saving the Hardware State48Restoring the Hardware State49Blt Engine Programming53BLT Engine Programming Considerations53When the Source and Destination Locations Overlap53Basic Graphics Data Considerations57Contiguous vs. Discontinuous Graphics Data57Source Data58Monochrome Source Data59Pattern Data60Destination Data62BLT Programming Examples63Pattern Fill -- A Very Simple BLT63Drawing Characters Using a Font Stored in System Memory66Initialization Registers69Standard VGA Registers69SMRAM Registers69SMRAM—System Management RAM Control Register (Device 0)69Display, I/O, GPIO, Clock, LCD, and Pixel Pipeline Registers722D Graphics Controller Registers (3CEh / 3CFh)732D CRT Controller Registers (3B4h/3D4h/3B5h/3D5h)73Initialization Values for VGA Registers74Frame Buffer Access77VGA and Extended VGA Registers79General Control & Status Registers79ST00(Input Status 080ST01(Input Status 181FCR(Feature Control82MSR(Miscellaneous Output83Sequencer Registers84SRX(Sequencer Index84SR00(Sequencer Reset85SR01(Clocking Mode86SR02(Plane/Map Mask87SR03(Character Font88SR04(Memory Mode Register89SR07(Horizontal Character Counter Reset90Graphics Controller Registers90GRX(GRX Graphics Controller Index Register90GR00(Set/Reset Register91GR01(Enable Set/Reset Register91GR02(Color Compare Register92GR03(Data Rotate Register92GR04(Read Plane Select Register93GR05(Graphics Mode Register93GR06(Miscellaneous Register96GR07(Color Don’t Care Register97GR08(Bit Mask Register97GR10(Address Mapping98GR11(Page Selector99GR[14:1F](Software Flags100Attribute Controller Registers101ARX(Attribute Controller Index Register101AR[00:0F](Palette Registers [0:F]102AR10(Mode Control Register102AR11(Overscan Color Register104AR12(Memory Plane Enable Register104AR13(Horizontal Pixel Panning Register105AR14(Color Select Register106VGA Color Palette Registers106DACMASK(Pixel Data Mask Register107DACSTATE(DAC State Register108DACRX(Palette Read Index Register108DACWX(Palette Write Index Register108DACDATA(Palette Data Register109CRT Controller Register109CRX(CRT Controller Index Register110CR00(Horizontal Total Register111CR01(Horizontal Display Enable End Register111CR02(Horizontal Blanking Start Register111CR03(Horizontal Blanking End Register112CR04(Horizontal Sync Start Register112CR05(Horizontal Sync End Register113CR06(Vertical Total Register114CR07(Overflow Register114CR08(Preset Row Scan Register117CR09(Maximum Scan Line Register118CR0A(Text Cursor Start Register119CR0B(Text Cursor End Register119CR0C(Start Address High Register120CR0D(Start Address Low Register121CR0E(Text Cursor Location High Register121CR0F(Text Cursor Location Low Register122CR10(Vertical Sync Start Register122CR11(Vertical Sync End Register123CR12(Vertical Display Enable End Register124CR13(Offset Register124CR14(Underline Location Register125CR15(Vertical Blanking Start Register126CR16(Vertical Blanking End Register126CR17(CRT Mode Control127CR18(Line Compare Register131CR22(Memory Read Latch Data Register131CR24( Test Register for Toggle State of Attribute Controller Register132CR30(Extended Vertical Total Register132CR31(Extended Vertical Display End Register133CR32(Extended Vertical Sync Start Register134CR33(Extended Vertical Blanking Start Register135CR35( Extended Horizontal Total Time Register136CR39(Extended Horizontal Blank Time Register136CR40(Extended Start Address Register137CR41(Extended Offset Register138CR42(Extended Start Address High Register138CR70(Interlace Control Register139CR80(I/O Control139CR81(Reserved140CR82(Blink Rate Control140Programming Interface141Reserved Bits and Software Compatibility141Overview141GC Register Programming142GC Instruction Streams142Instruction Use142Instruction Transport Overview142Instruction Parser143Ring Buffers (RB)144Ring Buffer Registers144Ring Buffer Initialization145Ring Buffer Use145Batch Buffers146Instruction Arbitration147Arbitration Rationale147Wait Instructions147Instruction Arbitration Points148Instruction Arbitration Rules148Batch Buffer Protected Mode148Instruction Format149Instruction Parser Instructions1492D Instructions1493D Instructions150Instruction Parser Instructions153Introduction153Instruction Descriptions153GFXCMDPARSER_NOP_IDENTIFICATION153GFXCMDPARSER_BREAKPOINT_INTERRUPT154GFXCMDPARSER_USER_INTERRUPT154GFXCMDPARSER_WAIT_FOR_EVENT155GFXCMDPARSER_FLUSH156GFXCMDPARSER_CONTEXT _SEL156GFXCMDPARSER _DEST_BUFFER_INFO157GFXCMDPARSER _FRONT_BUFFER_INFO158GFXCMDPARSER _Z_BUFFER_INFO159GFXCMDPARSER_REPORT_HEAD159GFXCMDPARSER_ARB_ON_OFF160GFXCMDPARSER_OVERLAY_FLIP1602D Instructions163BLTs To and From Cacheable Memory163BLT Engine Instructions163BLT Engine Instruction Definitions184Rendering Engine Instructions205GFXPRIMITIVE205Axis Aligned Rectangles205Primitive Winding Order205Position Mask206Bias206Primitive Rendering Instruction Format206Variable Length Vertex Formats for Rendering Instructions207GFXVERTEX208GFXRENDERSTATE_VERTEX_FORMAT209GFXBLOCK210Motion Vector Format213Non-pipelined State Variables213GFXRENDERSTATE_MAP_TEXELS214GFXRENDERSTATE_MAP_COORD_SETS215GFXRENDERSTATE_MAP_INFO217GFXRENDERSTATE_MAP_FILTER222GFXRENDERSTATE_MAP_LOD_LIMITS224GFXRENDERSTATE_MAP_LOD_CONTROL225GFXRENDERSTATE_MAP_PALETTE_LOAD226GFXRENDERSTATE_MAP_COLOR_BLEND_STAGES227GFXRENDERSTATE_MAP_ALPHA_BLEND_STAGES230GFXRENDERSTATE_COLOR_FACTOR232GFXRENDERSTATE_COLOR_CHROMA_KEY233GFXRENDERSTATE_SRC_DST_BLEND_MONO235GFXRENDERSTATE_Z_BIAS_ALPHA_FUNC_REF238GFXRENDERSTATE_LINE_WIDTH_CULL_SHADE_ MODE239GFXRENDERSTATE_BOOLEAN_ENA_1241GFXRENDERSTATE_BOOLEAN_ENA_2242GFXRENDERSTATE_FOG_COLOR243GFXRENDERSTATE_DRAWING_RECTANGLE_INFO243GFXRENDERSTATE_SCISSOR_ENABLE245GFXRENDERSTATE_SCISSOR_RECTANGLE_INFO246Stipple Pattern247GFXRENDERSTATE_ANTI_ALIASING248GFXRENDERSTATE_PROVOKING_VTX_PIXELIZATION_RULE249GFXRENDERSTATE_DEST_BUFFER_VARIABLES251Programming Hints/Rules253Clock Control Registers257Programming Notes257DCLK_0D—Display Clock 0 Divisor Register258DCLK_1D—Display Clock 1 Divisor Register259DCLK_2D—Display Clock 2 Divisor Register260LCD_CLKD—LCD Clock Divisor Register261DCLK_0DS—Display & LCD Clock Divisor Select Register262PWR_CLKC—Power Management and Miscellaneous Clock Control264Overlay Registers265OV0ADD—Overlay 0 Register Update Address Register267DOV0STA—Display/Overlay 0 Status Register268Gamma Correction269Memory Offset Registers274Overlay Buffer Pointer Registers274OBUF_0Y—Overlay Buffer 0 Y Pointer Register274OBUF_1Y—Overlay Buffer 1 Y Pointer Register275OBUF_0U—Overlay Buffer 0 U Pointer Register275OBUF_0V—Overlay Buffer 0 V Pointer Register276OBUF_1U—Overlay Buffer 1 U Pointer Register276OBUF_1V—Overlay Buffer 1 V Pointer Register277Overlay Stride Registers277OV0STRIDE—Overlay 0 Stride Register277Overlay Initial Phase Registers278YRGB_VPH—Y/RGB Vertical Phase Register278UV_VPH—UV Vertical Phase Register279HORZ_PH—Horizontal Phase Register279INIT_PH—Initial Phase Register280Overlay Destination Window Position/Size Registers281DWINPOS—Destination Window Position Register281DWINSZ—Destination Window Size Register281Overlay Source Size Registers282SWID—Source Width Register282SWIDQW—Source Width In QWords Register283SHEIGHT—Source Height Register284Overlay Scale Factor Registers285YRGBSCALE—Y/RGB Scale Factor Register285UVSCALE—UV Scale Factor Register286Overlay Color Correction Registers287OV0CLRC0—Overlay 0 Color Correction 0 Register287OV0CLRC1—Overlay 0 Color Correction 1 Register287Overlay Destination Color Key Registers288DCLRKV—Destination Color Key Value Register288DCLRKM—Destination Color Key Mask Register289Overlay Source Color Key Registers290SCLRKVH—Source Color Key Value High Register290SCLRKVL—Source Color Key Value Low Register291SCLRKM—Source Color Key Mask Register291Overlay Configuration Registers293OV0CONF—Overlay Configuration Register293OV0CMD—Overlay Command Register294Overlay Alpha Blend Window Position/Size Registers298AWINPOS—Alpha Blend Window Position Register298AWINSZ—Alpha Blend Window Size Register299Overlay Flip Instruction299Instruction, Memory, and Interrupt Control Registers301Instruction Control Registers301FENCE—Graphics Memory Fence Table Registers301PGTBL_CTL—Page Table Control Register303PGTBL_ER—Page Table Error Register304PGTBL_ERRMSK—Page Table Error Mask Register306RINGBUF—Ring Buffer Registers308HWS_PGA—Hardware Status Page Address Register310IPEIR—Instruction Parser Error Identification Register (debug)311IPEHR—Instruction Parser Error Header Register (debug)311INSTDONE—Instruction Stream Interface Done Register312NOPID—NOP Identification Register313INSTPM—Instruction Parser Mode Register314INSTPS—Instruction Parser State Register (debug)315BBP_PTR—Batch Buffer Parser Pointer Register (debug)317ABB_STR—Active Batch Buffer Start Address Register (debug)317ABB_END—Active Batch Buffer End Address Register (debug)318DMA_FADD—DMA Engine Fetch Address (debug)318MEM_MODE—Memory Interface Mode Register (debug)319Interrupt Control Registers320HWSTAM—Hardware Status Mask Register322IER—Interrupt Enable Register323IIR—Interrupt Identity Register324IMR—Interrupt Mask Register325ISR—Interrupt Status Register326Error Identity, Mask and Status Registers327Page Table Error handling in Intel® 815 Chipset327Resetting the Page Table Error328EIR—Error Identity Register329EMR—Error Mask Register329ESR—Error Status Register330Display Interface Control331FW_BLC—FIFO Watermark and Burst Length Control331LCD / TV-Out Register Description333HTOTAL—Horizontal Total Register333HBLANK—Horizontal Blank Register334HSYNC—Horizontal Sync Register335VTOTAL—Vertical Total Register336VBLANK—Vertical Blank Register337VSYNC—Vertical Sync Register338LCDTV_C—LCD/TV-Out Control Register339OVRACT—Overlay Active Register342BCLRPAT— Border Color Pattern Register342Local Memory Interface343DRT—DRAM Row Type343DRAMCL—DRAM Control Low344DRAMCH—DRAM Control High345I/O Control Registers347HVSYNC—HSYNC/VSYNC Control Register347GPIO Registers348GPIOA(General Purpose I/O Control Register A348GPIOB(General Purpose I/O Control Register B350Display And Cursor Registers353DISP_SL—Display Scan Line Count353DISP_SLC—Display Scan Line Count Range Compare354Pixel Pipeline Control355PIXCONF—Pixel Pipeline Configuration355BLTCNTL—BLT Control357SWF[1:3]—Software Flag Registers357DPLYBASE—Display Base Address Register358DPLYSTAS—Display Status Select Register359Hardware Cursor361CURCNTR—Cursor Control Register361CURBASE—Cursor Base Address Register362CURPOS—Cursor Position Register362Appendix A: Mode Parameters363Dimensioni: 1,98 MBPagine: 423Language: EnglishApri il manuale