Manuale UtenteSommarioPreface3Table of Contents4List of Illustrations18List of Tables23Sec. 1- Device Overview251.1 M68300 Family261.1.1 Organization271.1.2 Advantages271.2 Central Processor Unit271.2.1 CPU32281.2.2 Background Debug Mode281.3 On-Chip Peripherals291.3.1 System Integration Module291.3.2 Direct Memory Access Module311.3.3 Serial Module311.3.4 Timer Modules321.4 Power Consumption Management321.5 Physical331.6 Compact Disc-Interactive331.7 More Information34Sec. 2- Signal Descriptions352.1 Signal Index362.2 Address Bus382.2.1 Address Bus382.2.2 Address Bus382.3 Data Bus382.4 Function Codes392.5 Chip Selects392.6 Interrupt Request Level402.7 Bus Control Signals402.7.1 Data and Size Acknowledge402.7.2 Address Strobe402.7.3 Data Strobe412.7.4 Transfer Size412.7.5 Read/Write412.8 Bus Arbitration Signals412.8.1 Bus Request412.8.2 Bus Grant412.8.3 Bus Grant Acknowledge412.8.4 Read-Modify-Write Cycle422.9 Exception Control Signals422.9.1 Reset422.9.2 Halt422.9.3 Bus Error422.10 Clock Signals422.10.1 System Clock422.10.2 Crystal Oscillator432.10.3 External Filter Capacitor432.10.4 Clock Mode Select432.11 Instrumentation and Emulation Signals432.11.1 Instruction Fetch432.11.2 Instruction Pipe432.11.3 Breakpoint442.11.4 Freeze442.12 DMA Module Signals442.12.1 DMA Request442.12.2 DMA Acknowledge442.12.3 DMA Done442.13 Serial Module Signals452.13.1 Serial Crystal Oscillator452.13.2 Serial External Clock Input452.13.3 Receive DAta452.13.4 Transmit Data452.13.5 Clear to Send452.13.6 Request to Send452.13.7 Transmitter Ready452.13.8 Receiver Ready462.14 Timer Signals462.14.1 Timer Gate462.14.2 Timer Input462.14.3 Timer Output462.15 Test Signals472.15.1 Test Clock472.15.2 Test Mode Select472.15.3 Test Data In472.15.4 Test Data Out472.16 Synthesizer Power472.17 System Power and Ground472.18 Signal Summary47Sec. 3- Bus Operation503.1 Bus Transfer Signals503.1.1 Bus Control Signals513.1.2 Function Code Signals523.1.3 Address Bus533.1.4 Address Strobe533.1.5 Data Bus533.1.6 Data Strobe533.1.7 Bus Cycle Termination Signals533.2 Data Transfer Mechanism543.2.1 Dynamic Bus Sizing543.2.2 Misaligned Operands563.2.3 Operand Transfer Cases563.2.4 Bus Operation633.2.5 Synchronous Operation with DSACK633.2.6 Fast Termination Cycles643.3 Data Transfer Cycles653.3.1 Read Cycle653.3.2 Write cycle673.3.3 Read-Modify-Write Cycle683.4 CPU Space Cycles703.4.1 Breakpoint Acknowledge Cycle713.4.2 LPSTOP Broadcast Cycle723.4.3 Module Base Address Register Access763.4.4 Interrupt Acknowledge Bus Cycles763.5 Bus Exception Control Cycles813.5.1 Bus Errors833.5.2 Retry Operation853.5.3 Halt Operation873.5.4 Double Bus Fault883.6 Bus Arbitration893.6.1 Bus Request923.6.2 Bus Grant923.6.3 Bus Grant Acknowledge923.6.4 Bus Arbitration Control933.6.5 Show Cycles933.7 Reset Operation95Sec. 4- System Integration Module984.1 Module Overview984.2 Module Operation994.2.1 Module Base Address Register Operation994.2.2 System Configuration and Protection Operation1004.2.3 Clock Synthesizer Operation1064.2.4 Chip Select Operation1104.2.5 External Bus Interface Operation1124.2.6 Low-Power Stop1144.2.7 Freeze1144.3 Programming Model1154.3.1 Module Base Address Register1174.3.2 System Configuration and Protection Registers1184.3.3 Clock Synthesizer Control Register1254.3.4 Chip Select Registers1264.3.5 External Bus Interface Control1304.4 MC68340 Initialization Sequence1334.4.1 Startup1334.4.2 SIM40 Module Configuration1334.4.3 SIM40 Example Configuration Code135Sec. 5- CPU321385.1 Overview1385.1.1 Features1395.1.2 Virtual Memory1395.1.3 Loop Mode Instruction Execution1405.1.4 Vector Base Register1415.1.5 Exception Handling1415.1.6 Addressing Modes1425.1.7 Instruction Set1425.1.8 Processing States1445.1.9 Privilege States1445.2 Architecture Summary1455.2.1 Programming Model1455.2.2 Registers1475.3 Instruction Set1485.3.1 M68000 Family Compatibility1485.3.2 Instruction Format and Notation1495.3.3 Instruction Summary1525.3.4 Using the TBL Instructions1665.3.5 Nested Subroutine Calls1735.3.6 Pipeline Synchronization with the NOP Instruction1735.4 Processing States1735.4.1 State Transitions1745.4.2 Privilege Levels1745.5 Exception Processing1755.5.1 Exception Vectors1765.5.2 Processing of Specific Exceptions1805.5.3 Fault Recovery1895.5.4 CPU32 Stack Frames1975.6 Development Support2005.6.1 CPU32 Integrated Development Support2005.6.2 Background Debug Mode2026.5.3 Deterministic Opcode Tracking2245.7 Instruction Execution Timing2265.7.1 Resource Scheduling2265.7.2 Instruction Stream Timing Examples2315.7.3 Instruction Timing Tables234Sec. 6- DMA Controller Module2516.1 DMA Module Overview2526.2 DMA Module Signal Definitions2546.2.1 DMA Request2546.2.2 DMA Acknowledge2546.2.3 DMA Done2546.3 Transfer Request Generation2546.3.1 Internal Request Generation2546.3.2 External Request Generation2556.4 Data Transfer Modes2566.4.1 Single-Address Mode2566.4.2 Dual-Address Mode2626.5 Bus Arbitration2686.6 DMA Channel Operation2686.6.1 Channel Initialization and Startup2686.6.2 Data Transfers2696.6.3 Channel Termination2706.7 Register Description2726.7.1 Module Configuration Register2736.7.2 Interrupt Register2766.7.3 Channel Control Register2766.7.4 Channel Status Register2806.7.5 Function Code Register2826.7.6 Source Address Register2836.7.7 Destination Address Register2836.7.8 Byte Transfer Counter Register2846.8 Data Packing2856.9 DMA Channel Initialization Sequence2866.9.1 DMA Channel Configuration2866.9.2 DMA Channel Example Configuration Code288Sec. 7- Serial Module2967.1 Module Overview2977.1.1 Serial Communication Channels A & B2987.1.2 Baud Rate Generator Logic2987.1.3 Internal Channel Control Logic2987.1.4 Interrupt Control Logic2987.1.5 Comparison of Serial Module to MC686812997.2 Serial Module Signal Definitions2997.2.1 Crystal Input or External Clock3007.2.2 Crystal Output3007.2.3 External Input3017.2.4 Channel A Transmitter Serial Data Output3017.2.5 Channel A Receiver Serial Data Input3017.2.6 Channel B Transmitter Serial Data Output3017.2.7 Channel B Receiver Serial Data Input3017.2.8 Channel A Request-To-Send3017.2.9 Channel B Request-To-Send3017.2.10 Channel A Clear-To-Send3027.2.11 Channel B Clear-To-Send3027.2.12 Channel A Transmitter Ready3027.2.13 Channel A Receiver Ready3027.3 Operation3037.3.1 Baud Rate Generator3037.3.2 Transmitter and Receiver Operating Modes3037.3.3 Looping Modes3097.3.4 Multidrop Mode3107.3.5 Bus Operation3127.4 Register Description and Programming3127.4.1 Register Description3127.4.2 Programming3357.5 Serial Module Initialization Sequence3417.5.1 Serial Module Configuration3417.5.2 Serial Module Example Configuration Code342Sec. 8- Timer Modules3458.1 Module Overview3458.1.1 Timer and Counter Functions3468.1.2 Internal Control Logic3478.1.3 Interrupt Control Logic3488.2 Timer Modules Signal Definitions3488.2.1 Timer Input3498.2.2 Timer Gate3508.2.3 Timer Output3508.3 Operating Modes3508.3.1 Input Capture/Output Compare3508.3.2 Square-Wave Generator3528.3.3 Variable Duty-Cycle Square-Wave Generator3538.3.4 Variable-Width Single-Shot Pulse Generator3548.3.5 Pulse-Width Measurement3568.3.6 Period Measurement3578.3.7 Event Count3588.3.8 Timer Bypass3608.3.9 Bus Operation3618.4 Register Description3618.4.1 Module Configuration Register3628.4.2 Interrupt Register3648.4.3 Control Register3648.4.4 Status Register3678.4.5 Counter Register3698.4.6 Preload 1 Register3698.4.7 Preload 2 Register3708.4.8 Compare Register3708.5 Timer Module Initialization Sequence3718.5.1 Timer Module Configuration3718.5.2 Timer Module Example Configuration Code372Sec. 9- IEEE 1149.1 Test Access Port3769.1 Overview3769.2 Tap Controller3779.3 Boundary Scan Register3789.4 Instruction Register3849.4.1 Extest3859.4.2 Sample/Preload3859.4.3 Bypass3869.4.4 HI-Z3869.5 MC68340 Restrictions3869.6 Non-IEEE 1149.1 Operation387Sec. 10- Applications38810.1 Minimum System Configuration38810.1.1 Processor ClockCircuitry38810.1.2 Reset Circuitry39010.1.3 SRAM Interface39010.1.4 ROM Interface39110.1.5 Serial Interface39110.2 Memory Interface Information39210.2.1 Using an 8-Bit Boot ROM39210.2.2 Access Time Calculations39310.2.3 Calculating Frequency-Adjusted Output39410.2.4 Interfacing an 8-Bit Device to 16-Bit MEmory Using Single-Address DMA Mode39710.3 Power Consumption Considerations39710.3.1 MC68340 Power Reduction at 5V39810.3.2 MC68340V400Sec. 11- Electrical Characteristics40111.1 Maximum Ratings40111.2 Thermal Characteristics40111.3 Power Considerations40211.4 AC Electrical Specification Definitions40211.5 DC Electrical Specifications40511.6 AC Electrical Specifications Control Timing40611.7 AC Timing Specifications40811.8 DMA Module AC Electrical Specifications41911.9 Timer Module Electrical Specifications42011.10 Serial Module Electrical Specifications42211.11 IEEE1149.1 Electrical Specifications424Sec. 12- Ordering Information and Mechanical Data42612.1 Standard MC68340 Ordering Information42612.2 Pin Assignment - Ceramic Surface Mount42712.3 Package Dimensions431Index433A433B433C434D434E435F435G436H436I436J437L437M437N437O437P437R438S439T439U440V440W440X440Y441Z441Dimensioni: 2,44 MBPagine: 441Language: EnglishApri il manuale
